CS4341-CZZ Cirrus Logic Inc, CS4341-CZZ Datasheet
CS4341-CZZ
Specifications of CS4341-CZZ
Available stocks
Related parts for CS4341-CZZ
CS4341-CZZ Summary of contents
Page 1
... The features of the CS4341 are ideal for DVD players, CD players, set- top box and automotive systems. ORDERING INFORMATION CS4341-KS CS4341-CZZ, Lead Free CDB4341 SDA/CDIN AD0/CS MUTEC External ...
Page 2
... TABLE OF CONTENTS 1. CHARACTERISTICS AND SPECIFICATIONS ..................................................................................... 4 SPECIFIED OPERATING CONDITIONS .............................................................................................. 4 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 4 ANALOG CHARACTERISTICS (CS4341-KS/CZZ)............................................................................... 5 COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE........................................ 7 SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE........................................................ 10 SWITCHING CHARACTERISTICS - INTERNAL SERIAL CLOCK ..................................................... 11 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (I²C®) ..................................... 12 SWITCHING CHARACTERISTICS - CONTROL PORT INTERFACE (SPI™) ................................... 13 DC ELECTRICAL CHARACTERISTICS ...
Page 3
... Figure 14. Control Port Timing - I²C Mode ..................................................................................................12 Figure 15. Control Port Timing - SPI Mode .................................................................................................13 Figure 16. Typical Connection Diagram ......................................................................................................16 Figure 17. CS4341 Formats 0-1 - I² 24-Bit Data ..............................................................................18 Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data ...................................................................18 Figure 19. CS4341 Formats 3-6 - Right Justified ........................................................................................18 Figure 20. De-Emphasis Curve ...................................................................................................................19 Figure 21. I²C Buffer Example .....................................................................................................................21 Figure 22. I² ...
Page 4
... AGND = 0 V.) Symbol Min Nominal 3 2.7 Nominal 5 4.75 -KS/CZZ T -10 A (AGND = 0 V; all voltages with respect to AGND. Operation beyond Symbol VA I (Note IND stg CS4341 = 25°C.) A Nom Max Units 3.3 3.6 V 5.0 5.5 V °C - +70 Min Max Units -0.3 6 ±10 mA -0.3 VA+0 ...
Page 5
... ANALOG CHARACTERISTICS (CS4341-KS/CZZ) test signal is a 997 Hz sine wave at 0 dBFS; measurement bandwidth kHz; test load (see Figure 1).) Parameter Single-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise 18 to 24-Bit 16-Bit Double-Speed Mode Dynamic Range 18 to 24-Bit 16-Bit Total Harmonic Distortion + Noise ...
Page 6
... ANALOG CHARACTERISTICS (CS4341-KS/CZZ) Parameters Dynamic Performance for All Modes Interchannel Isolation (1 kHz) DC Accuracy Interchannel Gain Mismatch Gain Drift Analog Output Characteristics and Specifications Full-Scale Output Voltage Output Impedance Minimum AC-Load Resistance Maximum Load Capacitance Notes: 2. One-half LSB of triangular PDF dither is added to data. ...
Page 7
... De-emphasis is only available in Single-Speed Mode. DS298F5 Min to -0.05 dB corner corner 0 -0.02 0.5465 50 (Note kHz - kHz - Fs = 44.1 kHz - kHz - to -0.1 dB corner corner 0 -0.06 0.577 55 (Note kHz - kHz - CS4341 (The filter characteris- Typ Max Unit - 0.4535 Fs - 0.4998 Fs - +0. 9/ ±0.36/ +0.2/-0 +0.05/-0. +0/-0.22 ...
Page 8
... Figure 3. Single-Speed Stopband Rejection Figure 5. Single-Speed Transition Band (Detail) Figure 7. Double-Speed Stopband Rejection 8 Figure 4. Single-Speed Transition Band Figure 6. Single-Speed Passband Ripple Figure 8. Double-Speed Transition Band CS4341 DS298F5 ...
Page 9
... Figure 9. Double-Speed Transition Band (Detail) DS298F5 Figure 10. Double-Speed Passband Ripple CS4341 9 ...
Page 10
... SCLK rising to LRCK edge setup time SDIN valid to SCLK rising setup time SCLK rising to SDIN hold time LRCK SCLK SDATA 10 Single-Speed Mode Double-Speed Mode Single-Speed Mode Double-Speed Mode t slrs t slrd t sclkl t sdlrs Figure 11. Serial Input Timing (External SCLK) CS4341 Symbol Min Max 1.024 51 100 sclkl ...
Page 11
... MCLK / LRCK = 384 or 192 Notes: 6. The Duty Cycle must be 50% +/− 1/2 MCLK Period. 7. See section 4.2.1 for derived internal frequencies. *INTERNAL SCLK *INTERNAL SCLK * The SCLK pulses shown are internal to the CS4341. N equals MCLK divided by SCLK DS298F5 Symbol Single-Speed Mode Fs Fs ...
Page 12
... Repeated Start t high t t sud t sust low hdd Figure 14. Control Port Timing - I²C Mode CS4341 ® ) Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 300 4 SCL. fc Stop susp ...
Page 13
... CDIN DS298F5 Symbol f sclk t srs t (Note 10) spi t csh t css t scl t sch t dsu t (Note 11 (Note 12 (Note 12 srs t spi t css t scl t sch dsu t dh Figure 15. Control Port Timing - SPI Mode CS4341 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ ---------------- - MCLK - ns 1 ---------------- - MCLK 100 ns - ...
Page 14
... V; all voltages with respect to AGND.) Symbol Min kHz PSRR - (AGND = 0 V; all voltages with respect to AGND.) Symbol Min (AGND = 0 V; all voltages with respect to AGND.) Symbol CS4341 Typ Max Units µ µ 0 0. 0.45• 250 - kΩ 0. 250 - kΩ 0. ...
Page 15
... Power (Input) - Positive power for the analog, digital, and serial audio interface sections. MUTEC 16 Mute Control (Output) - Control signal for an optional mute circuit. DS298F5 RST MUTEC 1 16 SDATA AOUTA 2 15 SCLK LRCK 4 13 AGND MCLK 5 12 AOUTB SCL/CCLK 6 11 REF_GND SDA/CDIN AD0/CS FILT+ (Input/Output) - Input/Output for I²C data. Input for SPI data. CS4341 15 ...
Page 16
... AOUT A + Ω CS4341 M UTEC 16 9 FILT 0.1 µF .1 µF 1 µ REF_GND 3.3 µF Ω 560 12 AO UTB + Ω Figure 16. Typical Connection Diagram CS4341 +3 +5.0 V Audio O utput PTIO NAL MUTE CIRCUIT + 1 µF Audio O utput 560 π 4 Fs(R 560) L DS298F5 ...
Page 17
... Operation in the Internal Serial Clock mode is identical to operation with an external SCLK syn- chronized with LRCK; however, External SCLK mode is recommended for system clocking appli- cations. DS298F5 Single-Speed Mode Double-Speed Mode Table 1. CS4341 Speed Modes MCLK (MHz) 384x 512x 12.2880 16.3840 16.9344 22 ...
Page 18
... LRCK, SCLK and SDATA, see Figures 17 through 19. Left C ha nnel SDATA - MSB Figure 17. CS4341 Formats 0-1 - I² 24-Bit Data SDATA - MSB Figure 18. CS4341 Format 2 - Left Justified up to 24-Bit Data LRCK Left Channel SCLK SDATA - LSB MSB 18 Digital Interface Format Selection Left Justified 24 Right Justified Bits 18 Bits ...
Page 19
... Popguard Transient Control ® The CS4341 uses Popguard technology to minimize the effects of output transients during power-up and power-down. This technology, when used with external DC-blocking capacitors in series with the audio outputs, minimizes the audio transients commonly produced by single-ended single-supply converters activated inside the DAC when RST is enabled/disabled and requires no other external control, aside from choosing the appropriate DC-blocking capacitors ...
Page 20
... Grounding and Power Supply Arrangements As with any high resolution converter, the CS4341 requires careful attention to power supply and ground- ing arrangements if its potential performance realized. Figure 16 shows the recommended power arrangements, with VA connected to a clean supply. If the ground planes are split between digital ground and analog ground, REF_GND & ...
Page 21
... I²C rise time specification. This prevents the use of com- mon I²C configurations with a resistor pull-up. A workaround is achieved by placing a Schmitt Trig- ger buffer, a 74HC14 for example, on the SCL line just prior to the CS4341. This will not affect the operation of the I²C bus as pin input only. ...
Page 22
... If the INCR bit is set to 0 and further I²C reads from other registers are desired necessary to repeat the procedure detailed from step further reads from other registers are de- sired, initiate a STOP condition to the bus. 22 MAP 001000 AD0 W ACK ACK 1-8 Figure 22. I²C Write CS4341 DATA ACK 1-8 Stop DS298F5 ...
Page 23
... Repeated START or Aborted W RITE Figure 23. I²C Read CHIP ADDRESS MAP 0010000 MSB R/W MAP = Memory Address Pointer Figure 24. Control Port Timing, SPI Mode CS4341 Data 1-8 Data 1-8 R ACK ACK (pointed to by MAP) (pointed to by MAP) DATA LSB byte 1 byte n ...
Page 24
... DEFAULT 3h Channel A Volume MUTEA Control 0 DEFAULT 4h Channel B Volume MUTEB Control 0 DEFAULT DIF2 DIF1 DIF0 DEM1 SCZ1 SCZ0 ATAPI4 ATAPI3 VOLA6 VOLA5 VOLA4 VOLA3 VOLB6 VOLB5 VOLB4 VOLB3 CS4341 DEM1 POR PDN ATAPI2 ATAPI1 ATAPI0 VOLA2 VOLA1 VOLA0 VOLB2 VOLB1 VOLB0 DS298F5 ...
Page 25
... Mute Control pin will go active during the mute period. The muting function is affected, similar to vol- ume control changes, by the Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. DS298F5 Reserved Reserved BIT DIF1 DIF0 DEM1 BIT 7 CS4341 Reserved MCLKDIV Reserved DEM0 POR PDN ...
Page 26
... I² 16-bit data, 32Fs Internal SCLK Left Justified 24-bit data, Right Justified, 24-bit data Right Justified, 20-bit data Right Justified, 16-bit data Right Justified, 18-bit data Identical to Format 1 Table 5. Digital Interface Format BIT 2-3 BIT 1 BIT 0 CS4341 ) through . 17 19 Format FIGURE ...
Page 27
... The zero cross function is independently monitored and implemented for each channel. DS298F5 ATAPI4 ATAPI3 BIT 5-6 CS4341 2 1 ATAPI2 ATAPI1 0 0 BIT 7 0 ATAPI0 1 27 ...
Page 28
... ATAPI CHANNEL MIXING AND MUTING (ATAPI) Default = 01001 - AOUTA = Left Channel, AOUTB = Right Channel (Stereo) Function: The CS4341 implements the channel mixing functions of the ATAPI CD-ROM specification. Refer to Table 6 and Figure 25 for additional information. ATAPI4 ATAPI3 ATAPI2 BIT 0-4 ATAPI1 ...
Page 29
... Cross bits in the Transition and Mixing Control (address 02h) register. The MUTEC will go active dur- ing the mute period if the Mute function is enabled for both channels. DS298F5 A Channel Volume Control Σ B Channel Volume Control Figure 25. ATAPI Block Diagram VOLx4 VOLx3 CS4341 MUTE AoutA Σ MUTE AoutB VOLx2 VOLx1 VOLx0 ...
Page 30
... Soft and Zero Cross bits in the Transition and Mixing Control (address 02h) register. All volume settings less than - 94 dB are equivalent to enabling the Mute bit. Binary Code 0000000 0010100 0101000 0111100 1011010 30 Decimal Value Table 7. Example Digital Volume Settings CS4341 Volume Setting 0 dB -20 dB -40 dB -60 dB -90 dB DS298F5 ...
Page 31
... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. DS298F5 CS4341 31 ...
Page 32
... JEDEC #: MS-012 Controling Dimension is Millimeters CS4341 c ∝ L MILLIMETERS MIN NOM MAX 1.35 1.63 1.75 0.10 0.15 0.25 0.33 0.41 0.51 0.19 0.20 0.25 9 ...
Page 33
... Symbol (for multi-layer boards) (for multi-layer boards END VIEW L MILLIMETERS NOM MAX -- -- 1.10 -- 0.15 0.90 0.95 0.245 0.30 5.00 5.10 6.40 6.50 4.40 4.50 -- 0.65 BSC -- 0.60 0.70 4° 8° Min Typ Max θ θ CS4341 ∝ NOTE 2 Units °C/Watt °C/Watt 33 ...
Page 34
... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. 34 Changes www.cirrus.com/corporate/contacts/sales.cfm CS4341 DS298F5 ...