CS43L21-CNZ Cirrus Logic Inc, CS43L21-CNZ Datasheet

no-image

CS43L21-CNZ

Manufacturer Part Number
CS43L21-CNZ
Description
IC DAC 24BIT 98DB 96KHZ 32QFN
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS43L21-CNZ

Package / Case
32-QFN
Number Of Bits
24
Data Interface
Serial
Number Of Converters
2
Voltage Supply Source
Analog and Digital, Dual ±
Operating Temperature
-10°C ~ 70°C
Mounting Type
Surface Mount
Conversion Rate
96 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
1.8 V or 2.5 V
Operating Temperature Range
+ 70 C
Mounting Style
SMD/SMT
Number Of Dac Outputs
2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1282 - BOARD EVAL FOR CS43L21 DAC
Power Dissipation (max)
-
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1187

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS43L21-CNZ
Manufacturer:
TI
Quantity:
10
Part Number:
CS43L21-CNZ
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS43L21-CNZR
Manufacturer:
CIRRUS
Quantity:
20 000
Part Number:
CS43L21-CNZR
Manufacturer:
CIRRUS
Quantity:
18 453
Advance Product Information
FEATURES
Mode or I
SPI Software
98 dB Dynamic Range (A-wtd)
-86 dB THD+N
Headphone Amplifier - GND Centered
Digital Signal Processing Engine
Programmable Peak-Detect and Limiter
Pop and Click Suppression
Serial Audio
Control Data
http://www.cirrus.com
Beep Generator
Hardware
On-Chip Charge Pump Provides -VA_HP
No DC-Blocking Capacitor Required
46 mW Power Into Stereo 16 Ω @ 1.8 V
88 mW Power Into Stereo 16 Ω @ 2.5 V
-75 dB THD+N
Bass & Treble Tone Control, De-Emphasis
PCM Mix w/Independent Vol Control
Master Digital Volume Control and Limiter
Soft Ramp & Zero Cross Transitions
Tone Selections Across Two Octaves
Separate Volume Control
Programmable On & Off Time Intervals
Continuous, Periodic or One-Shot Beep
Selections
Reset
Input
Mode
2
C &
Low Power, Stereo Digital to Analog Converter
1.8 V to 3.3 V
Configuration
Register
Generator
Beep
This document contains information for a new product.
Cirrus Logic reserves the right to modify this product without notice.
Processing
Engine
Digital
Signal
Copyright © Cirrus Logic, Inc. 2006
(All Rights Reserved)
1.8 V to 2.5 V
MUX
MUX
SYSTEM FEATURES
∆Σ Modulator
24-bit Conversion
4 kHz to 96 kHz Sample Rate
Multi-bit Delta Sigma Architecture
Low Power Operation
Variable Power Supplies
Power Down Management
Software Mode (I²C
Hardware Mode (Stand-Alone Control)
Digital Routing/Mixes:
Flexible Clocking Options
Multibit
Stereo Playback: 12.93 mW @ 1.8 V
1.8 V to 2.5 V Digital & Analog
1.8 V to 3.3 V Interface Logic
Mono Mixes
Master or Slave Operation
High-Impedance Digital Output Option (for
easy MUXing between DAC and Other
Data Sources)
Quarter-Speed Mode - (i.e. Allows 8 kHz Fs
while maintaining a flat noise floor up to
16 kHz)
Capacitor DAC
Capacitor DAC
Switched
and Filter
Switched
and Filter
®
& SPI
1.8 V to 2.5 V
Headphone
Amp - GND
Headphone
Amp - GND
Centered
Centered
CS43L21
Charge
Pump
Control)
Right HP Out
Left HP Out
DS723A1
JULY '06

Related parts for CS43L21-CNZ

CS43L21-CNZ Summary of contents

Page 1

... Modulator Engine Capacitor DAC MUX This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. Copyright © Cirrus Logic, Inc. 2006 (All Rights Reserved) CS43L21 ® ™ & SPI Control) 1 2.5 V Headphone Switched ...

Page 2

... Smart Phones Wireless Headsets 2 GENERAL DESCRIPTION The CS43L21 is a highly integrated, 24-bit, 96 kHz, low power stereo DAC. Based on multi-bit, delta-sigma modulation, it allows infinite sample rate adjustment be- tween 4 kHz and 96 kHz. The DAC offers many features suitable for low power, portable system applications. ...

Page 3

... Recommended Power-Down Sequence ........................................................................................ 32 4.9 Software Mode ............................................................................................................................... 33 4.9.1 SPI Control ............................................................................................................................ 33 4.9.2 I²C Control ............................................................................................................................. 33 4.9.3 Memory Address Pointer (MAP) ............................................................................................ 35 4.9.3.1 Map Increment (INCR) ............................................................................................... 35 5. REGISTER QUICK REFERENCE ........................................................................................................ 36 6. REGISTER DESCRIPTION .................................................................................................................. 39 6.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 39 DS723A1 CS43L21 3 ...

Page 4

... Auto Detect Enabled ....................................................................................................................... 57 8.2 Auto Detect Disabled ...................................................................................................................... 58 9. PCB LAYOUT CONSIDERATIONS ..................................................................................................... 59 9.1 Power Supply, Grounding ............................................................................................................... 59 9.2 QFN Thermal Pad .......................................................................................................................... 59 10. DIGITAL FILTERS .............................................................................................................................. 60 11. PARAMETER DEFINITIONS .............................................................................................................. 61 12. PACKAGE DIMENSIONS ................................................................................................................. 62 THERMAL CHARACTERISTICS ........................................................................................................ 62 13. ORDERING INFORMATION ............................................................................................................. 63 14. REFERENCES .................................................................................................................................... 63 15. REVISION HISTORY ......................................................................................................................... 63 4 CS43L21 DS723A1 ...

Page 5

... Figure 25.Power Dissipation vs. Output Power into Stereo 16 Ω ......................................................................56 Figure 26.Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) .......................................... 56 Figure 27.Passband Ripple ....................................................................................................................... 60 Figure 28.Stopband ................................................................................................................................... 60 Figure 29.Transition Band ......................................................................................................................... 60 Figure 30.Transition Band (Detail) ............................................................................................................ 60 LIST OF TABLES Table 1. I/O Power Rails ............................................................................................................................. 8 Table 2. Hardware Mode Feature Summary ............................................................................................. 23 Table 3. MCLK/LRCK Ratios .................................................................................................................... 29 DS723A1 CS43L21 5 ...

Page 6

... Charge Pump Cap Negative Node (Input) - Negative node for the external charge pump capacitor. Negative Voltage From Charge Pump (Output) - Negative voltage rail for the internal analog head- 9 VSS_HP phone section CS43L21 Pin Description CS43L21 TSTO 24 TSTO 23 TSTO 22 TSTO 21 TSTO 20 TSTO 19 TSTO 18 TSTO 17 DS723A1 ...

Page 7

... Serial Clock (Input/Output) - Serial clock for the serial audio interface. 32 SDIN Serial Audio Data Input (Input) - Input for two’s complement serial audio data. - Thermal Pad Thermal relief pad for optimized heat dissipation. See DS723A1 CS43L21 “QFN Thermal Pad” on page 59. 7 ...

Page 8

... TSTO Input/Output (M/S) SDIN Input 8 Driver - - 1 3.3 V, CMOS/Open Drain - - 1 3.3 V, CMOS 1 3.3 V, CMOS 1 3.3 V, CMOS - Table 1. I/O Power Rails CS43L21 Receiver 1 3 3.3 V, with Hysteresis 1 3.3 V, with Hysteresis 1 3 3 3 3 3 3.3 V DS723A1 ...

Page 9

... CS43L21 Note 2 : For best response to Fs/2 : MCLK This circuitry is intended for applications where the SCLK CS43L21 connects directly to an unbalanced output of the device. For internal routing applications please see the LRCK DAC Analog Output Characteristics section for loading limitations. SDIN RESET ...

Page 10

... AGND VQ DGND Note 2 : This circuitry is intended for applications where the CS 43L21 connects directly to an unbalanced output of the device . For internal routing applications please see the DAC Analog Output Characteristics section for loading limitations . CS43L21 +1.8V or +2.5V Headphone Out Left & Right R C ...

Page 11

... DS723A1 Symbol VA VA_HP VD VL Commercial - CNZ T A Automotive - DNZ Symbol VA, VA_HP Analog VD Digital VL Serial/Control Port Interface I (Note IND stg CS43L21 Min Nom Max Units 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2.63 V 1.65 1.8 1.89 V 2.37 2.5 2 ...

Page 12

... Refer to Table “Line Output Voltage Characteristics” on (Note 5) Refer to Table “Headphone Output Power Characteristics” 16 Ω kΩ - 0.1 - ±100 (Note (Note CS43L21 = 10 kΩ for the line output 1.8V (nominal) Max Min Typ Max - -78 - -88 ...

Page 13

... Refer to Table “Line Output Voltage Characteristics” on (Note 5) Refer to Table “Headphone Output Power Characteristics” 16 Ω kΩ - 0.1 - ±100 (Note (Note CS43L21 = 10 kΩ for the for the headphone output 1.8V (nominal) Max Min Typ Max - -73 ...

Page 14

... kΩ (see 2.5V (nominal 1.8V (nominal) Min Typ Max Min - 2.05 - 1.41 1.95 2. (See (Note CS43L21 Figure 3). Typ Max Unit 1. DS723A1 ...

Page 15

... High gain settings at certain VA and VA_HP supply levels may 55. reflect the recommended minimum resistance and maximum capacitance re- L AOUTx 51 Ω C 0.022 µF L AGND Figure 3. Headphone Output Test Load CS43L21 = 10 pF (see Figure 3 1.8V (nominal) Min Typ Max - ...

Page 16

... SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 16 (Note 8) to -0.05 dB corner corner kHz Fs = 44.1 kHz kHz (Note 10) (Note 11) Quarter-Speed Mode Half-Speed Mode Single-Speed Mode Double-Speed Mode CS43L21 Min Typ Max -0.01 - +0. 0.4780 0 - 0.4996 0.5465 - ...

Page 17

... s(SD-SK MSB // All Speed Modes , RESET should be held low after the power supplies and clocks are set- CS43L21 for typical MCLK frequencies d(MSB s(SD-SK MSB // CS43L21 // MSB-1 Symbol Min Max MCLK F - ---------------- - s 128 45 55 1/t - 64• d(MSB s(SD-SK ...

Page 18

... Repeated Start Start t high t hdst sud t sust low hdd Figure 6. Control Port Timing - I²C CS43L21 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 3450 , of SCL. fc Stop susp ...

Page 19

... RST CS CCLK CDIN DS723A1 ™ CONTROL PORT Symbol f sck t srs t css t csh t scl t sch t dsu t (Note 14 (Note 15 (Note 15 srs css sch scl dsu dh Figure 7. Control Port Timing - SPI Format CS43L21 Min Max Units 0 6.0 MHz µs 1 100 ns - 100 ns t csh ...

Page 20

... High-Level Output Voltage ( 100 µA) Low-Level Output Voltage (I OL High-Level Input Voltage Low-Level Input Voltage 18. See “Digital I/O Pin Characteristics” on page 8 20 (Note 17) 1 kHz Symbol (Note 18) for serial and control port power rails. CS43L21 Min Typ Max - 0.5• -0.8• ...

Page 21

... RESET pin 25 held LO, all clocks and data lines are held LO. 21. RESET pin 25 held HI, all clocks and data lines are held HI. 22. VL current will slightly increase in master mode. DS723A1 Power Ctl. Registers 02h 03h i VA_HP 1.8 2 1.8 2 1.8 1.66 2.5 2. 1.8 2.77 2.5 3.21 CS43L21 Typical Current (mA (Note 22) ( 0.01 0. ...

Page 22

... Architecture The CS43L21 is a highly integrated, low power, 24-bit audio D/A comprised of stereo digital-to-analog converters (DAC) designed using multi-bit delta-sigma techniques. The DAC operates at an oversampling ratio of 128Fs. The D/A operates in one of four sample rate speed modes: Quarter, Half, Single and Dou- ble ...

Page 23

... Soft Ramp Disabled Zero Cross (Selectable) Disabled Mix Disabled Beep Disabled Disabled Data Input (PCM) to DAC PCMA = L; PCMB = R DAC (64xFs)/7 Table 2. Hardware Mode Feature Summary CS43L21 “Recommended Power- Table 2 shows a list Stand-Alone Control Note - - - - - - see Section “MCLKDIV2” pin 2 4.4 on page 28 see Section “ ...

Page 24

... INV_DACA BASS[3:0] INV_DACB TREB[3:0] DAC_SNGVOL +12.0dB/-10.5dB AMUTE 1.5dB steps VOL Figure 8. Output Architecture 9. The de-emphasis feature is included to accommodate audio recordings that 42. Setting LO HI CS43L21 DATA_SEL[1:0] PDN_DACA PDN_DACB HP_GAIN[2:0] Headphone Switched Amp - GND Capacitor DAC 01 Centered and Filter 00 Charge Pump CHRG_FREQ[3:0] ...

Page 25

... Frequency & Timing Configuration (Address 12h)” on page Software (Address 13h)” on page Controls: DS723A1 dB T1=50 µs 0dB µ Frequency 3.183 kHz 10.61 kHz Figure 9. De-Emphasis Curve 49. 46, “Beep Configuration & Tone Configuration (Address 14h)” on page 47 CS43L21 45, “Beep Off Time & Volume 25 ...

Page 26

... Software “Limiter Release Rate Register (Address 1Ah)” on page Controls: 1Bh)” on page 26 OFFTIME[2:0] Figure 10. Beep Configuration Options 48. 52, “DAC Control (Address 09h)” on page 42 CS43L21 ... 51, “Limiter Attack Rate Register (Address DS723A1 ...

Page 27

... CUSHION ARATE[5:0] RRATE[5:0] Figure 11. Peak Detect & Limiter “Typical Connection Diagram (Software Mode)” on page 9 10, is required on the analog outputs. This allows the DAC 41, 49. CS43L21 AOUTx_VOL[7:0] volume control should NOT be adjusted manually when Limiter is enabled. CUSH[2:0] and the “Typical Con- “ ...

Page 28

... Figure 2 on page 10 “Charge Pump Frequency (Address 21h)” on page , “DAC Control (Address 09h)” on page Pin 47 kΩ Pull-down “M/S” pin 29 47 kΩ Pull-up “MCLKDIV2” pin 2 CS43L21 for the recommended capacitor 53. 42. Setting Selection Slave Master LO No Divide ...

Page 29

... Speed MCLKDIV2 Single ÷ 2 Speed Half ÷ 4 Speed Quarter ÷ 8 Speed Figure 12. Master Mode Timing CS43L21 SSM DSM 128, 192, 256, 384, 128, 192, 256, 384 512, 768 256, 384, 512*, 768* 128, 192, 256*, 384 LRCK Output (Equal to Fs) 10 ...

Page 30

... SDIN AOUTA / AINxA 30 CS42L51 Transmitting Device #2 3ST_SP SCLK/LRCK Receiving Device Figure 13. Tri-State SCLK/LRCK “Switching Specifications - Serial Port” on page 16 41. Setting LO Left-Justified Interface HI I²S Interface Figure 14. I²S Format CS43L21 Figures 14-17 illustrate for exact Selection AOUTB / AINxB DS723A1 MSB ...

Page 31

... Bring RESET low if the analog or digital supplies drop below the recommended operating condition to prevent power glitch related issues. DS723A1 Figure 15. Left-Justified Format Figure 16. Right-Justified Format (DAC only) 33 valid write sequence to the control port is not made within approximately CS43L21 MSB AOUTB / AINxB AOUTB Figure 17 on page 32 ...

Page 32

... ERROR: MCLK/LRCK ratio change alone settings. ERROR: MCLK removed Analog Output Freeze 1. Aout bias = last audio sample. 2. DAC Modulators stop operation. 3. Audible pops. Figure 17. Initialization Flow Chart CS43L21 Standby Mode Yes 1. No audio signal generated. 2. Control Port Registers retain settings Valid ...

Page 33

... All other transitions of SDA occur while the clock is low. The first byte sent to the CS43L21 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). The upper 6 bits of the 7-bit address field are fixed at 100101. To communicate with a ...

Page 34

... MAP BYTE DATA INCR ACK ACK Figure 19. Control Port Timing, I²C Write STOP MAP BYTE CHIP ADDRESS (READ INCR ACK START Figure 20. Control Port Timing, I²C Read CS43L21 DATA +1 DATA + ACK ACK DATA DATA +1 DATA + AD0 ACK ACK ACK STOP NO STOP DS723A1 ...

Page 35

... The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and SPI writes. If INCR is set to 1, MAP will auto-increment after each byte is read or written, allowing block reads or writes of successive registers. DS723A1 CS43L21 35 ...

Page 36

... Reserved DEEMPH Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved CS43L21 Rev_ID2 Rev_ID1 Rev_ID0 Reserved Reserved Note 1(See Note 1(See Note 2 on page 2 on page 39) 39) 39) Reserved Reserved MCLKDIV2 Reserved Reserved Reserved Reserved Reserved ...

Page 37

... AOUTB_ VOL6 VOL5 VOL4 Reserved PCMB1 PCMB0 MAX1 MAX0 CUSH2 LIM_RRATE LIM_RRATE LIM_RRATE LIM_ARATE5 LIM_ARATE4 LIM_ARATE3 LIM_ARATE2 LIM_ARATE1 LIM_ARATE0 Reserved Reserved Reserved CS43L21 Reserved Reserved PCMMIXA PCMMIXA VOL3 VOL2 VOL1 PCMMIXB PCMMIXB VOL3 VOL2 VOL1 ONTIME3 ONTIME2 ONTIME1 BPVOL3 BPVOL2 BPVOL1 ...

Page 38

... CHRG_ CHRG_ FREQ3 default Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved SPEB_OVFL SPEA_OVFL PCMA_OVFL PCMB_OVFL CHRG_ CHRG_ FREQ2 FREQ1 FREQ0 CS43L21 Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved 1 Reserved 0 Reserved 0 Reserved 0 Reserved 0 DS723A1 ...

Page 39

... Chip_ID2 Chip I.D. (Chip_ID[4:0]) Default: 11011 Function: I.D. code for the CS43L21. Permanently set to 11011. Chip Revision (Rev_ID[2:0]) Default: 001 Function: CS43L21 revision level. Revision B is coded as 001. Revision A is coded as 000. 6.2 Power Control 1 (Address 02h Reserved PDN_DACB PDN_DACA Notes: 1 ...

Page 40

... When enabled and the device is configured as a master, the SCLK/LRCK signals are placed in a high-im- pedance output state. If the serial port is configured as a slave, SCLK/LRCK are configured as inputs. MCLK Divide By 2 (MCLKDIV2) Default Disabled 1 - Divide 3-ST_SP Reserved above). CS43L21 Reserved Reserved MCLKDIV2 Table 3 on page 29. The DS723A1 ...

Page 41

... DS723A1 DAC_DIF1 DAC_DIF0 Description 30 DAC_ INV_PCMB SNGVOL CS43L21 2 1 Reserved Reserved Reserved Figure 15 on page page page 3217 on page page 3217 on page page 3217 on page page 3217 on page INV_PCMA DACB_MUTE DACA_MUTE ...

Page 42

... Signal Processing Engine to DAC 10 - Reserved 11 - Reserved Function: Selects the digital signal source for the DAC. Note: Certain functions are only available when the “Signal Processing Engine to DAC” option is selected using these bits Reserved DEEMPH CS43L21 “Line Output Voltage Characteris- 15 AMUTE DAC_SZC1 DAC_SZC0 DS723A1 ...

Page 43

... The requested level change will occur after a timeout period between 1024 and 2048 sample periods (21 42 kHz sample rate) if the signal does not encounter a zero crossing. The zero cross function is independently monitored and imple- mented for each channel. Note: The LIM_SRDIS bit is ignored. DS723A1 CS43L21 43 ...

Page 44

... DACX Soft and Zero Cross bits (DACX_SZC[1:0]) from +12 to -51.5 dB. Levels are decoded as described in the table above PCMMIXx_ PCMMIXx_ VOL4 VOL3 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -51.5 dB CS43L21 PCMMIXx_ PCMMIXx_ PCMMIXx_ VOL2 VOL1 VOL0 DS723A1 ...

Page 45

... Fs, but is fixed at the nominal Fs within each speed mode. Refer page 26 for single-, multiple- and continuous-beep configurations using the REPEAT and BEEP bits. DS723A1 FREQ0 ONTIME3 Pitch Time 86 ms ··· 5.2 s CS43L21 ONTIME2 ONTIME1 ONTIME0 Figure 10 on Figure 45 ...

Page 46

... BEEP bits. Levels are decoded as described in the table above BPVOL4 BPVOL3 1.23 s 2.58 s 3.90 s 5.20 s 6.60 s 8.05 s 9.35 s Volume Setting +12.0 dB ··· ··· -50 dB for single-, multiple- and continuous-beep configurations using the REPEAT CS43L21 BPVOL2 BPVOL1 BPVOL0 DS723A1 ...

Page 47

... The treble corner frequency is user selectable as shown above. Bass Corner Frequency (BASS_CF[1:0]) Default 100 200 250 Hz Function: The bass corner frequency is user-selectable as shown above. DS723A1 TREB_CF1 TREB_CF0 for a description of each configuration option. Figure 10 on page 26 CS43L21 BASS_CF1 BASS_CF0 TC_EN for a description of each con- 47 ...

Page 48

... The level of the shelving bass gain filter is set by Bass Gain Level. The level can be adjusted in 1.5 dB in- crements from +10.5 to -10.5 dB TREB0 BASS3 Gain Setting +12.0 dB ··· +1 -1.5 dB ··· -10.5 dB Gain Setting +12.0 dB ··· +1 -1.5 dB ··· -10.5 dB CS43L21 BASS2 BASS1 BASS0 DS723A1 ...

Page 49

... PCMA[1:0] AOUTA ----------- - Function: Implements mono mixes of the left and right channels as well as a left/right channel swap. DS723A1 Volume Setting +12.0 dB ··· -0.5 dB -1.0 dB ··· -102 dB ··· -102 PCMB0 Reserved PCMB[1:0] AOUTB ----------- - CS43L21 Reserved Reserved Reserved 49 ...

Page 50

... The Limiter uses this cushion as a hysteresis point for the input signal as it maintains the signal below the maximum as well as below the cushion setting. This provides a more natural sound as the limiter attacks and releases CUSH2 CUSH1 CS43L21 CUSH0 LIM_SRDIS LIM_ZCDIS DS723A1 ...

Page 51

... When set to 0, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on the spe- cific channel indicating clipping. The other channels will not be affected. When set to 1, the peak signal limiter will limit the maximum signal amplitude to prevent clipping on both channels in response to any single channel indicating clipping. DS723A1 RRATE4 RRATE3 CS43L21 RRATE2 RRATE1 RRATE0 51 ...

Page 52

... On initial power up and application of clocks, this bit will be high as the serial port re-synchronizes. 52 Release Time Fastest Release ··· Slowest Release ARATE4 ARATE3 Attack Time Fastest Attack ··· Slowest Attack SPEB_OVFL PCMA_OVFL PCMB_OVFL “Serial Port Clocking” section on page 28“Serial Port Clock- CS43L21 ARATE2 ARATE1 ARATE0 Reserved Reserved DS723A1 ...

Page 53

... Alters the clocking frequency of the charge pump in 1/(N+2) fractions of the DAC oversampling rate, 128Fs, should the switching frequency interfere with other system frequencies such as those in the AM radio band. Note: Distortion performance may be affected. DS723A1 CHRG_FREQ Reserved 1 0 Frequency 64xFs ---------------- - CS43L21 Reserved Reserved Reserved 53 ...

Page 54

... W 40m 50m 60m 70m 80m W CS43L21 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 23 mW into single 16 Ω and 46 mW into stereo 16 Ω with THD dB). ...

Page 55

... W 30m 35m 40m 45m 50m 55m 60m W CS43L21 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 22 mW into single 32 Ω and 44 mW into stereo 32 Ω with THD dB). ...

Page 56

... Input test signal is a 997 Hz sine wave; Power Consumption Mode 6 - Stereo Playback w/16 Ω load. HP_GAIN = 1.1430. Best efficiency is realized when the amplifier outputs maximum power. VA_HP = VA = 1.8 V Figure 25. Power Dissipation vs. Output Power into Stereo 16 Ω VA_HP = VA = 1.8 V Figure 26. Power Dissipation vs. Output Power into Stereo 16 Ω (Log Detail) 56 CS43L21 DS723A1 ...

Page 57

... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS43L21 2048x* 3072x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x* 1536x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x* 768x* 16.3840 24 ...

Page 58

... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS43L21 2048x 3072x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x 1536x 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x 768x 16.3840 24 ...

Page 59

... QFN Thermal Pad The CS43L21 is available in a compact QFN package. The under side of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...

Page 60

... FILTERS Figure 27. Passband Ripple Figure 29. Transition Band 60 CS43L21 Figure 28. Stopband Figure 30. Transition Band (Detail) DS723A1 ...

Page 61

... The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. Offset Error The deviation of the mid-scale transition (111...111 to 000...000) from the ideal. Units in mV. DS723A1 CS43L21 61 ...

Page 62

... JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS43L21 b e Pin #1 Corner L D2 Bottom View MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 5.00 BSC 3.30 3.35 5.00 BSC 3 ...

Page 63

... I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS723A1 Package Pb-Free Grade Temp Range Commercial -10 to +70° C 32L-QFN Yes Automotive -40 to +85° Changes CS43L21 Container Order # Rail CS43L21-CNZ Tape & Reel CS43L21-CNZR Rail CS43L21-DNZ Tape & Reel CS43L21-DNZR - - CDB43L21 63 ...

Related keywords