IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part NumberCS4382A-CQZ
DescriptionIC DAC 8CH 114DB 192KHZ 48LQFP
ManufacturerCirrus Logic Inc
CS4382A-CQZ datasheets
 


Specifications of CS4382A-CQZ

Package / Case48-LQFPNumber Of Bits24
Data InterfaceSerialNumber Of Converters8
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)680mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Conversion Rate192 KSPSResolution24 bit
Interface TypeSerialOperating Supply Voltage5 V
Operating Temperature Range+ 85 CMaximum Power Dissipation390 mW
Mounting StyleSMD/SMTNumber Of Dac Outputs8
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time-Other names598-1061
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114 dB, 192 kHz 8-Channel D/A Converter
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Up to 192 kHz Sample Rates
114 dB Dynamic Range
-100 dB THD+N
®
Direct Stream Digital
(DSD
On-chip 50 kHz Filter
Matched PCM and DSD Analog Output Levels
Selectable Digital Filters
Volume Control with 1 dB Step Size and Soft
Ramp
Low Clock-jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control & Serial Ports
C o n tro l & S erial A u d io P o rt
S u p p lies = 1.8 V to 5 V
H ard w are Mo d e o r
2
I
C /S P I S o ftw are Mo d e
C o n tro l D ata
R es et
P C M S erial
A u d io In p u t
D S D A u d io
In p u t
http://www.cirrus.com
Description
The CS4382A is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
1 dB step size volume control, ATAPI channel mixing,
selectable fast and slow digital interpolation filters fol-
lowed by an oversampled, multi-bit delta-sigma
modulator which includes mismatch shaping technolo-
gy that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capac-
itor stage and low-pass filter with differential analog
outputs.
) Mode
The CS4382A also has a proprietary DSD processor
which allows for 50 kHz on-chip filtering without an in-
termediate decimation stage. The CS4382A is available
in a 48-pin LQFP package in both Commercial (-40°C to
+85°C) and Automotive grades (-40°C to +105°C). The
CDB4382A Customer Demonstration board is also
available for device evaluation and implementation sug-
gestions. Please see
for complete details.
The CS4382A accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems including SACD players, A/V re-
ceivers,
processors, sound cards, and automotive audio
systems.
D ig ital S u p p ly = 2.5 V
R e giste r/H a rdwa re
C onfigura tion
V olume
Multi-bit ∆Σ
D igita l
C ontrols
F ilte rs
Modula tors
8
D S D P roce ssor
-50 kH z filte r
Copyright © Cirrus Logic, Inc. 2009
(All Rights Reserved)
CS4382A
“Ordering Information” on page 48
digital
TV’s,
mixing
consoles,
A n alo g S u p p ly = 5 V
Inte rna l V olta ge
R e fe re nce
S witch-C a p
D ifferen tial
8
D A C a nd
O u tp u ts
A na log F ilte rs
8
E xte rna l Mute
Mu te S ig n als
C ontrol
2
effects
JAN '09
DS618F2

CS4382A-CQZ Summary of contents

  • Page 1

    ... Please see for complete details. The CS4382A accepts PCM data at sample rates from 4 kHz to 216 kHz, DSD audio data, and delivers excel- lent sound quality. These features are ideal for multi- channel audio systems including SACD players, A/V re- ...

  • Page 2

    ... REGISTER QUICK REFERENCE ........................................................................................................ 32 6. REGISTER DESCRIPTION .................................................................................................................. 33 6.1 Mode Control 1 (Address 01h) ....................................................................................................... 33 6.1.1 Control Port Enable (CPEN) .................................................................................................. 33 6.1.2 Freeze Controls (FREEZE) ................................................................................................... 33 6.1.3 Master Clock Divide Enable (MCLKDIV) ............................................................................... 33 6.1.4 DAC Pair Disable (DACx_DIS) .............................................................................................. 33 6.1.5 Power Down (PDN) ............................................................................................................... 34 6.2 Mode Control 2 (Address 02h) ....................................................................................................... 34 2 CS4382A DS618F2 ...

  • Page 3

    ... Mute (MUTE) ......................................................................................................................... 40 6.7.2 Volume Control (XX_VOL) .................................................................................................... 41 6.8 Chip Revision (Address 12h) ......................................................................................................... 41 6.8.1 Part Number ID (PART) [Read Only] .................................................................................... 41 6.8.2 Revision ID (REV) [Read Only] ............................................................................................. 41 7. FILTER PLOTS ..................................................................................................................................... 42 8. PARAMETER DEFINITIONS ................................................................................................................ 46 9. PACKAGE DIMENSIONS .................................................................................................................... 47 10. ORDERING INFORMATION .............................................................................................................. 48 11. REFERENCES .................................................................................................................................... 48 12. REVISION HISTORY .......................................................................................................................... 49 DS618F2 CS4382A 3 ...

  • Page 4

    ... Figure 36.Quad-Speed (fast) Stopband Rejection .................................................................................... 44 Figure 37.Quad-Speed (fast) Transition Band .......................................................................................... 44 Figure 38.Quad-Speed (fast) Transition Band (detail) .............................................................................. 45 Figure 39.Quad-Speed (fast) Passband Ripple ........................................................................................ 45 Figure 40.Quad-Speed (slow) Stopband Rejection ................................................................................... 45 Figure 41.Quad-Speed (slow) Transition Band ......................................................................................... 45 Figure 42.Quad-Speed (slow) Transition Band (detail) ............................................................................. 45 Figure 43.Quad-Speed (slow) Passband Ripple ....................................................................................... 45 4 CS4382A DS618F2 ...

  • Page 5

    ... Table 2. Digital Interface Format, Stand-Alone Mode Options .................................................................. 22 Table 3. Mode Selection, Stand-Alone Mode Options .............................................................................. 22 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ........................................................... 22 Table 5. Digital Interface Formats - PCM Mode ........................................................................................ 34 Table 6. Digital Interface Formats - DSD Mode ........................................................................................ 35 Table 7. ATAPI Decode ............................................................................................................................ 39 Table 8. Example Digital Volume Settings ................................................................................................ 41 DS618F2 CS4382A 5 ...

  • Page 6

    ... DSDA2 36 1 DSDB1 2 35 DSDA1 GND 5 32 MCLK 6 CS4382A SDIN1 8 29 SCLK TST 27 SDIN2 11 26 TST Pin Description CS4382A AOUTA2- AOUTA2+ AOUTB2+ AOUTB2- VA GND AOUTA3- AOUTA3+ AOUTB3+ AOUTB3- AOUTA4- AOUTA4+ DS618F2 ...

  • Page 7

    ... DSD-Enable (Input) - When held at logic ‘1’ the device will enter DSD Mode (Stand-Alone mode only). DSDA1 3 DSDB1 2 DSDA2 1 DSDB2 48 Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSDA3 47 DSDB3 46 DSDA4 45 DSDB4 44 DS618F2 Pin Description ® Mode as shown in the Typical Connection Diagram. ™ Mode. CS4382A 7 ...

  • Page 8

    ... VA Digital Internal Power VD VLS Control Port Interface Power VLC Any Pin Except Supplies I in Serial Data Port Interface V IND-S Control Port Interface V IND stg CS4382A Min Typ Max Units 4.75 5.0 5.25 V 2.37 2.5 2.63 V 1.71 5.0 5.25 V 1.71 5.0 5.25 ...

  • Page 9

    ... A-weighted 108 Unweighted 105 16-bit A-weighted (Note 2) Unweighted 24-bit 0 dB -20 dB -60 dB THD+N 16-bit 0 dB - kHz) V 128%•V FS (Note 3) Z OUT I OUTmax QMAX and includes attenuation due CS4382A = 25 C; Full-Scale 997 Hz ° A Typ Max 114 - 111 - - -100 - -51 - ...

  • Page 10

    ... A-weighted Unweighted 16-bit A-weighted (Note 2) Unweighted 24-bit 0 dB -20 dB -60 dB THD+N 16-bit 0 dB - kHz) V 128%•V FS (Note 3) Z OUT I OUTmax QMAX CS4382A ; Tested under max ac-load resis- (Note 1) 19; Measurement Min Typ Max 105 114 - 102 111 - - -100 - -51 - ...

  • Page 11

    ... Valid with the recommended capacitor values on FILT+ and VQ as shown in DS618F2 Symbol Normal Operation, VA VD= 2 Interface Current, VLC VLS 2.5 V Normal Operation (Note 6) Power-down θ Multi-layer JA θ Two-layer JA θ kHz) PSRR (60 Hz) CS4382A Min Typ Max Units - µ µ µA - 200 - - 470 520 ...

  • Page 12

    ... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 6.15/Fs to -0.01 dB corner corner kHz -0.01 .635 (Note 10 7.1/Fs Section 7. “Filter Plots” on page CS4382A Typ Max Unit - .454 Fs - .499 Fs - +0. ±0. ±0. ±0. .430 Fs - .499 ...

  • Page 13

    ... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 5.4/Fs to -0.01 dB corner corner kHz -0.01 .868 (Note 10 6.6/Fs Min corner kHz -0.05 27 CS4382A (Note 8) Typ Max Unit - 0.417 Fs - 0.499 Fs - +0. ±0. ±0. ±0. .296 Fs - .499 Fs - +0.01 ...

  • Page 14

    ... MUTEC Low-level Output Voltage 13. Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch- up. 14 Symbol (Note 13 Serial I Control I Serial I Control I Control I Control I/O = 1 max CS4382A Min Typ Max Units µ ± 30% V ...

  • Page 15

    ... After powering up, RST should be held low until after the power supplies and clocks are settled. 15. See Table 1 on page 21 LRCK SCLK SDINx DS618F2 = 30 pF) L (Note 14) (Note 15) Single-speed Mode Double-speed Mode Quad-speed Mode for suggested MCLK frequencies lcks sckh MSB Figure 1. Serial Audio Interface Timing CS4382A Symbol Min Max 1 - 1.024 55 108 s F 100 216 ...

  • Page 16

    ... DSDxx Figure 2. Direct Stream Digital - Serial Audio Input Timing pF) L Symbol Min 40 t 160 sclkl t 160 sclkh (64x Oversampled) 1.024 (128x Oversampled) 2.048 t 20 sdlrs t 20 sdh t sclkh t sclkl t t sdlrs sdh CS4382A Typ Max Unit - 3.2 MHz - 6.4 MHz - - DS618F2 ...

  • Page 17

    ... high t t sud t sust hdd Figure 3. Control Port Timing - I²C Format CS4382A Min Max Unit - 100 kHz 500 - ns 4.7 - µs 4.0 - µs 4.7 - µs 4.0 - µs 4.7 - µ µs 250 - µs ...

  • Page 18

    ... L Symbol f sclk t srs (Note 17) t spi t csh t css t scl t sch t dsu (Note 18 (Note 19 (Note 19 css t scl t sch dsu t dh Figure 4. Control Port Timing - SPI Format CS4382A Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...

  • Page 19

    ... MUTEC1 44 DSDB4 MUTEC234 42 DSD_SCLK 19 RST 15 SCL/CCLK 16 SDA/CDIN 17 ADO/CS Note* FILT+ 18 VLC 0.1 µF GND GND TST CS4382A + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning 30 and Muting 28 Analog Conditioning ...

  • Page 20

    ... DSDB4 DSD AOUTB4- Note Optional 47 KΩ 42 MUTEC234 M3(DSD_SCLK Mode RST 18 VLC 0.1 µF GND GND 5 31 CS4382A + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting Mute 41 Drive 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning ...

  • Page 21

    ... The Left/Right Clock (LRCK) determines which channel is currently being input on SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. The CS4382A can be configured in Hardware Mode by the M0, M1, M2, M3, and DSD_EN pins and in Software Mode through I²C or SPI. ...

  • Page 22

    ... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate CS4382A FORMAT FIGURE 0 ...

  • Page 23

    ... Figure 10. Format 3 - Right-Justified 24-bit Data DS618F2 Figures + LSB MSB + LSB MSB Figure 8. Format 1 - I² 24-bit Data Figure 9. Format 2 - Right-Justified 16-bit Data CS4382A 7-12. Data is clocked into the DAC on the Right Channel + LSB Right Channel + LSB Right Channel Right Channel 7 ...

  • Page 24

    ... Oversampling Modes The CS4382A operates in one of three oversampling modes based on the input sample rate. Mode selection is determined by the DSD_EN, M3, and M2 pins in Hardware Mode or the FM bits in Software Mode. Single- speed mode supports input sample rates kHz and uses a 128x oversampling ratio. Double-speed Mode supports input sample rates up to 100 kHz and uses an oversampling ratio of 64x ...

  • Page 25

    ... Fs over 44,100. -10dB 4.7 ATAPI Specification The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to tion. Left Chan nel Audio D ata ...

  • Page 26

    ... The Typical Connection Diagram shows the recommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4382A should be con- nected to the analog ground plane. ...

  • Page 27

    ... In these de- signs, the pull-up and pull-down resistors have been especially chosen to meet the input high/low threshold when used with the MMUN2111 and MMUN2211 internal bias resistances DS618F2 Figure 15. Full-Scale Output Figure 16. Recommended Output Filter CS4382A 3.85 V 2.5 V 1.15 V 3. ...

  • Page 28

    ... Hardware Mode settings). 4. Set the PDN bit to 0. This will initiate the power-up sequence, which lasts approximately 50 µs. 28 Figure 17. Recommended Mute Circuitry Section 4.1. In this state, the registers are reset to the default CS4382A Section 4.1. In this state, the DS618F2 ...

  • Page 29

    ... START condition and follow the procedure detailed from step further writes to other registers are desired, initiate a STOP condition to the bus. DS618F2 Figure 18 for the clock to data relationship). There pin. Pin AD0 4.14.1) is set to 1, repeat the previous step until all the desired registers CS4382A 29 ...

  • Page 30

    ... If the INCR bit (see Section are written, then bring CS high. 30 Section 4.14. I²C read is the first operation performed on the 1-8 Figure 18. Control Port Timing, I²C Mode 4.14.1) is set to 1, repeat the previous step until all the desired registers CS4382A 1-8 S top DS618F2 ...

  • Page 31

    ... INCR Reserved Reserved 0 0 4.16 INCR (Auto Map Increment Enable) Default = ‘0’ Disabled 1 - Enabled 4.16.1 MAP4-0 (Memory Address Pointer) Default = ‘00000’ DS618F2 0011000 byte 1 Figure 19. Control Port Timing, SPI Mode MAP4 MAP3 CS4382A LSB byte MAP2 MAP1 MAP0 ...

  • Page 32

    ... P3ATAPI4 P3ATAPI3 P3ATAPI2 P3ATAPI1 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 P4ATAPI4 P4ATAPI4 P4ATAPI2 P4ATAPI1 A4_VOL6 A4_VOL5 A4_VOL4 B4_VOL6 B4_VOL5 B4_VOL4 PART3 PART2 PART1 CS4382A Reserved Reserved Reserved AMUTE Reserved Reserved DEM1 DEM0 INV_B2 INV_A2 INV_B1 P1ATAPI0 FM1 A1_VOL3 A1_VOL2 A1_VOL1 B1_VOL3 ...

  • Page 33

    ... When the bit is set, the respective DAC channel pair (AOUTAx and AOUTBx) will remain in a reset state advised that changes to these bits be made while the power-down (PDN) bit is enabled to eliminate the possibility of audible artifacts. DS618F2 DAC4_DIS DAC3_DIS CS4382A DAC2_DIS DAC1_DIS PDN ...

  • Page 34

    ... Left-Justified 24-bit data I² 24-bit data Right-Justified, 16-bit data Right-Justified, 24-bit data Right-Justified, 20-bit data Right-Justified, 18-bit data Reserved Reserved Table 5. Digital Interface Formats - PCM Mode DIF0 Reserved DESCRIPTION CS4382A 2 1 Reserved Reserved Reserved 0 0 Figures 7-12. Format FIGURE DS618F2 0 0 ...

  • Page 35

    ... DSD data with a 2x MCLK to DSD data rate 128x oversampled DSD data with a 3x MCLK to DSD data rate 128x oversampled DSD data with a 4x MCLK to DSD data rate 128x oversampled DSD data with a 6x MCLK to DSD data rate RMP_UP MUTEC+/- CS4382A AMUTE Reserved MUTEC ...

  • Page 36

    ... The quiescent voltage on the output will be retained, and the Mute Control pin will go active during the mute period. The muting function is affected, similar to volume control changes, by the Soft and Zero Cross bits in the Mode Control 3 register. 36 Section 4.11. Once reset has been released, the MUTEC out- CS4382A DS618F2 ...

  • Page 37

    ... This bit selects how the data is effected prior to and after the change of the filter val- ues. When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp DS618F2 FILT_SEL Reserved Section 2. Figure 13) CS4382A Section DEM1 DEM0 RMP_DN ...

  • Page 38

    ... Control Bytes when this function is disabled. The volume on both AOUTAx and AOUTBx are deter- mined by the A Channel Attenuation and Volume Control Bytes (per A-B pair), and the B Channel Bytes are ignored when this function is enabled INV_A3 INV_B2 PxATAPI2 PxATAPI1 CS4382A INV_A2 INV_B1 INV_A1 PxATAPI0 PxFM1 PxFM0 DS618F2 ...

  • Page 39

    ... ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4382A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 DS618F2 Table 7 and Figure 14 ATAPI1 ...

  • Page 40

    ... The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bit xx_VOL4 xx_VOL3 CS4382A xx_VOL2 xx_VOL1 xx_VOL0 DS618F2 ...

  • Page 41

    ... Chip Revision (Address 12h PART4 PART3 PART2 0 1 6.8.1 Part Number ID (PART) [Read Only] 01110 - CS4382A 6.8.2 Revision ID (REV) [Read Only] 000 - Revision A 001 - Revision B Function: This read-only register can be used to identify the model and revision number of the device. DS618F2 Decimal Value 0 ...

  • Page 42

    ... Figure 23. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 25. Single-Speed (slow) Transition Band CS4382A 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...

  • Page 43

    ... Figure 29. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 31. Double-Speed (fast) Passband Ripple CS4382A 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...

  • Page 44

    ... Figure 35. Double-Speed (slow) Passband Ripple 100 120 0.2 0.7 0.8 0.9 1 Figure 37. Quad-Speed (fast) Transition Band CS4382A 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...

  • Page 45

    ... Figure 41. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 43. Quad-Speed (slow) Passband Ripple CS4382A 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 0.8 Frequency(normalized to Fs) 0.04 0.06 0.08 ...

  • Page 46

    ... Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Error The deviation from the nominal full-scale analog output for a full-scale digital input. Gain Drift The change in gain value with temperature. Units in ppm/°C. 46 CS4382A DS618F2 ...

  • Page 47

    ... Nominal pin pitch is 0.50 mm Controlling dimension is mm. JEDEC Designation: MS022 CS4382A A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...

  • Page 48

    ... The I²C Bus Specification: Version 2.0 , Philips Semiconductors, December 1998 http://www.semiconductors.philips.com. 48 Package Pb-Free Grade Commercial -40°C to +85°C 48-pin YES LQFP Automotive -40°C to +105° http://www.cirrus.com. CS4382A Temp Range Container Order # Tray CS4382A-CQZ Tape & Reel CS4382A-CQZR Tray CS4382A-DQZ Tape & Reel CS4382A-DQZR - - CDB4382A DS618F2 ...

  • Page 49

    ... Polarity (MUTEC+/-)” on page DS618F2 Changes “DAC Analog Characteristics - Automotive (-DQZ)” on page “DAC Analog Characteristics - Automotive (-DQZ)” on page “DAC Pair Disable (DACx_DIS)” on page 34. “Mode Select” on page 9. 10. 11. 14. “IMPORTANT NOTICE” on page 50 “Pin Description” on page 27. 36. CS4382A 10. 10. 33. 21 ...

  • Page 50

    ... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. Direct Stream Digital is a registered trademark of Sony Kabushiki Kaisha TA Sony Corporation. DSD is a trademark of Sony Kabushiki Kaisha TA Sony Corporation 50 www.cirrus.com. CS4382A DS618F2 ...