CS4382A-CQZ Cirrus Logic Inc, CS4382A-CQZ Datasheet
CS4382A-CQZ
Specifications of CS4382A-CQZ
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CS4382A-CQZ Summary of contents
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Features Advanced Multi-bit Delta Sigma Architecture 24-bit Conversion Up to 192 kHz Sample Rates 114 dB Dynamic Range -100 dB THD+N ® Direct Stream Digital (DSD On-chip 50 kHz Filter Matched PCM and DSD Analog Output ...
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TABLE OF CONTENTS 1. PIN DESCRIPTION ................................................................................................................................. 6 2. CHARACTERISTICS AND SPECIFICATIONS ...................................................................................... 8 RECOMMENDED OPERATING CONDITIONS .................................................................................... 8 ABSOLUTE MAXIMUM RATINGS ........................................................................................................ 8 DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) ............................................................. 9 DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) ........................................................... 10 ...
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Digital Interface Format (DIF) ................................................................................................ 34 6.3 Mode Control 3 (Address 03h) ....................................................................................................... 35 6.3.1 Soft Ramp and Zero Cross Control (SZC) ............................................................................ 35 6.3.2 Single Volume Control (SNGLVOL) ...................................................................................... 36 6.3.3 Soft Volume Ramp-Up After Error (RMP_UP) ...................................................................... ...
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LIST OF FIGURES Figure 1.Serial Audio Interface Timing ...................................................................................................... 15 Figure 2.Direct Stream Digital - Serial Audio Input Timing ........................................................................ 16 Figure 3.Control Port Timing - I²C Format ................................................................................................. 17 Figure 4.Control Port Timing - SPI Format ................................................................................................ 18 Figure ...
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LIST OF TABLES Table 1. Common Clock Frequencies ....................................................................................................... 21 Table 2. Digital Interface Format, Stand-Alone Mode Options .................................................................. 22 Table 3. Mode Selection, Stand-Alone Mode Options .............................................................................. 22 Table 4. Direct Stream Digital (DSD), Stand-Alone Mode Options ........................................................... 22 ...
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PIN DESCRIPTION LRCK(DSD_EN) Pin Name # Digital Power (Input) - Positive power supply for the digital section. Refer to the Recom mended Operating Conditions for appropriate voltages. GND 5,31 Ground (Input) - Ground reference. Should be connected ...
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Pin Name # Quiescent Voltage (Output) - Filter connection for internal quiescent voltage. VQ must be capacitively coupled to analog ground, as shown in the Typical Connection Diagram. The nom- inal voltage level is specified in the Analog Characteristics and ...
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CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONS (GND = 0 V; all voltages with respect to ground.) Parameters DC Power Supply Serial Data Port Interface Power Ambient Operating Temperature (power applied) ABSOLUTE MAXIMUM RATINGS (GND = 0 V; all voltages ...
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DAC ANALOG CHARACTERISTICS - COMMERCIAL (-CQZ) Test Conditions (unless otherwise specified VLS = VLC = 2 input sine wave ; Tested under max ac-load resistance; Valid with FILT+ and VQ capacitors as ...
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DAC ANALOG CHARACTERISTICS - AUTOMOTIVE (-DQZ) Test Conditions (unless otherwise specified 4.75 to 5.25 V; VLS = 1.71 to 5.25 V; VLC = 1. 2. ...
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POWER AND THERMAL CHARACTERISTICS Parameters Power Supplies Power Supply Current (Note 4) (Note 5) (Note 6) Power-down State (all supplies) Power Dissipation (Note 4) Package Thermal Resistance Power Supply Rejection Ratio (Note 7) Notes: 4. Current consumption increases with increasing ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE The filter characteristics have been normalized to the sample rate (Fs) and can be referenced to the desired sam- ple rate by multiplying the given characteristic by Fs. See Note 12. Parameter Combined ...
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COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE (CONTINUED) Parameter Single-Speed Mode - 48 kHz Passband (Note 9) Frequency Response Stop Band Stop-band Attenuation Group Delay De-emphasis Error (Note 11) (Relative to 1 kHz) Double-Speed Mode - 96 kHz Passband (Note ...
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DIGITAL CHARACTERISTICS Parameters Input Leakage Current Input Capacitance High-level Input Voltage Low-level Input Voltage Low-level Output Voltage (I = -1.2 mA) OL Maximum MUTEC Drive Current MUTEC High-level Output Voltage MUTEC Low-level Output Voltage 13. Any pin except supplies. Transient ...
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SWITCHING CHARACTERISTICS - PCM (Inputs: Logic 0 = GND, Logic 1 = VLS, C Parameters RST pin Low Pulse Width MCLK Frequency MCLK Duty Cycle Input Sample Rate - LRCK LRCK Duty Cycle SCLK Duty Cycle SCLK High Time SCLK ...
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SWITCHING CHARACTERISTICS - DSD (Logic 0 = AGND = DGND; Logic 1 = VLS; C Parameter MCLK Duty Cycle DSD_SCLK Pulse Width Low DSD_SCLK Pulse Width High DSD_SCLK Frequency DSD_A / _B valid to DSD_SCLK rising setup time DSD_SCLK rising ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - I²C FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter SCL Clock Frequency RST Rising Edge to Start Bus Free Time Between Transmissions Start Condition Hold Time (prior to first clock ...
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SWITCHING CHARACTERISTICS - CONTROL PORT - SPI FORMAT (Inputs: Logic 0 = GND, Logic 1 = VLC, C Parameter CCLK Clock Frequency RST Rising Edge to CS Falling CCLK Edge to CS Falling CS High Time Between Transmissions CS Falling ...
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TYPICAL CONNECTION DIAGRAM +2.5 V 220 Ω PCM Digital Audio Source 470 Ω +1 470 Ω DSD Audio Source Micro- Controller +1 Note*: Necessary for I control port operation Figure 5. ...
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V DSD Note VLS PCM Digital Audio Source +1 DSD Audio Source Stand-Alone Mode Configuration +1 Figure 6. Typical Connection Diagram, Hardware Mode µF 0.1 µ ...
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APPLICATIONS The CS4362A serially accepts two’s-complement formatted PCM data at standard audio sample rates including 48, 44.1, and 32 kHz in SSM, 96, 88.2, and 64 kHz in DSM, and 192, 176.4, and 128 kHz in QSM. Audio data ...
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M1 M0 (DIF1) (DIF0) Left-justified 24-bit data 0 0 I² 24-bit data 0 1 Right-justified, 16-bit Data 1 0 Right-justified, 24-bit Data 1 1 Table 2. Digital Interface Format, Stand-Alone Mode Options M3 M2 (DEM) Single-speed ...
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Digital Interface Formats The serial port operates as a slave and supports the I²S, Left-justified, and Right-justified digital interface formats with varying bit depths from shown in rising edge. Left Channel LRCK SCLK SDINx +5 ...
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LRCK Left Channel SCLK SDINx clocks Figure 11. Format 4 - Right-Justified 20-bit Data LRCK Left Channel SCLK SDINx ...
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In Software Mode, the required de-emphasis filter coefficients for 32 kHz, 44.1 kHz kHz are selected via the de-emphasis control bits. In Hardware Mode, only the 44.1 kHz coefficient is available (enabled through the M2 pin). If the ...
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Direct Stream Digital (DSD) Mode In Stand-alone Mode, DSD operation is selected by holding DSD_EN(LRCK) high and applying the DSD data and clocks to the appropriate pins. The M[2:0] pins set the expected DSD rate and MCLK ratio. In ...
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AOUT+ AOUT- Full-Scale Output Level= (AOUT+) - (AOUT-)= 6.7 Vpp 4.11 Mute Control The Mute Control pins go active during power-up initialization, reset, muting the MCLK-to-LRCK ratio is incorrect. These pins are intended to be used as control ...
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Recommended Power-Up Sequence 4.12.1 Hardware Mode 1. Hold RST low until the power supplies and configuration pins are stable, and the master and left/right clocks are locked to the appropriate frequencies, as discussed in registers are reset to the ...
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MAP Auto Increment The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads ...
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I²C Read section further reads from other registers are de- sired, initiate a STOP condition to the bus ...
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Memory Address Pointer (MAP INCR Reserved Reserved 0 0 4.16 INCR (Auto Map Increment Enable) Default = ‘0’ Disabled 1 - Enabled 4.16.1 MAP4-0 (Memory Address Pointer) Default = ‘00000’ DS617F1 MAP4 ...
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REGISTER QUICK REFERENCE Addr Function 7 01h Mode Control 1 CPEN 0 default 02h Mode Control 2 Reserved 0 default 03h Mode Control 3 SZC1 1 default 04h Filter Control Reserved 0 default 05h Invert Control Reserved 0 default ...
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REGISTER DESCRIPTION Note: All registers are read/write in I²C Mode and write only in SPI, unless otherwise noted. 6.1 Mode Control 1 (Address 01h CPEN FREEZE MCLKDIV 0 0 6.1.1 Control Port Enable (CPEN) Default = 0 ...
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Power Down (PDN) Default = Disabled 1 - Enabled Function: The entire device will enter a low-power state when this function is enabled, and the contents of the control registers are retained in this mode. The ...
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DSD Mode: The relationship between the oversampling ratio of the DSD audio data and the required master clock-to-DSD-data-rate is defined by the Digital Interface Format pins. DIF2 DIF1 DIFO ...
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Single Volume Control (SNGLVOL) Default = Disabled 1 - Enabled Function: The individual channel volume levels are independently controlled by their respective Volume Control Bytes when this function is disabled. The volume on all channels is ...
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Mute Pin Control (MUTEC1, MUTEC0) Default = Six mute control signals 01 One mute control signal 11 - Three mute control signals Function: Selects how the internal mute control signals are routed to the ...
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When this bit is enabled, the DAC will ramp down the volume prior to a filter-mode change and ramp from mute to the original volume value after a filter-mode change according to the settings of the Soft and Zero ...
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ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4362A implements the channel mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...
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Functional Mode (FM) Default = Single-Speed Mode ( kHz sample rates Double-Speed Mode (50 to 100 kHz sample rates Quad-Speed Mode (100 to 200 kHz sample rates Direct ...
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Volume Control (XX_VOL) Default = 0 (No attenuation) Function: The Digital Volume Control registers allow independent control of the signal levels increments from 0 to -127 dB. Volume settings are decoded as shown in mented as ...
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FILTER PLOTS 0 −20 −40 −60 −80 −100 −120 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) Figure 19. Single-Speed (fast) Stopband Rejection 0 −1 −2 −3 −4 −5 −6 −7 −8 −9 −10 0.45 0.46 0.47 0.48 0.49 0.5 ...
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Frequency(normalized to Fs) Figure 25. Single-Speed (slow) Transition Band (detail 100 120 0.4 0.5 0.6 0.7 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 31. Double-Speed (slow) Stopband Rejection 0.45 0.46 0.47 0.48 0.49 0.5 0.51 Frequency(normalized ...
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Frequency(normalized to Fs) Figure 37. Quad-Speed (fast) Transition Band (detail 100 120 0.1 0.2 0.3 0.4 0.5 ...
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PARAMETER DEFINITIONS Total Harmonic Distortion + Noise (THD+N) The ratio of the rms value of the signal to the rms sum of all other spectral components over the specified bandwidth (typically kHz), including distortion components. ...
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PACKAGE DIMENSIONS 48L LQFP PACKAGE DRAWING D1 D DIM MIN A --- A1 0.002 B 0.007 D 0.343 D1 0.272 E 0.343 E1 0.272 e* 0.016 L 0.018 µ 0.000° DS617F1 ∝ L INCHES ...
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INFORMATION Product Description 114 dB, 192 kHz 6- CS4362A channel D/A Converter CDB4362A CS4362A Evaluation Board 11.REFERENCES 1. How to Achieve Optimum Performance from Delta-Sigma A/D & D/A Converters , by Steven Harris. Paper presented at the 93rd Convention ...
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HISTORY Release Updated output impedance spec in PP1 Improved interchannel isolation spec in PP2 Corrected package type. Corrected register description in Added note to “Digital Interface Format (DIF)” on page Added PCM mode format changeable in reset only to ...
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Contacting Cirrus Logic Support For all product questions and inquiries, contact a Cirrus Logic Sales Representative. To find the one nearest you IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this ...