IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part NumberCS4382A-CQZ
DescriptionIC DAC 8CH 114DB 192KHZ 48LQFP
ManufacturerCirrus Logic Inc
CS4382A-CQZ datasheets
 


Specifications of CS4382A-CQZ

Package / Case48-LQFPNumber Of Bits24
Data InterfaceSerialNumber Of Converters8
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)680mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Conversion Rate192 KSPSResolution24 bit
Interface TypeSerialOperating Supply Voltage5 V
Operating Temperature Range+ 85 CMaximum Power Dissipation390 mW
Mounting StyleSMD/SMTNumber Of Dac Outputs8
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time-Other names598-1061
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4.13
Recommended Procedure for Switching Operational Modes
For systems where the absolute minimum in clicks and pops is required, it is recommended that the MUTE
bits are set prior to changing significant DAC functions (such as changing sample rates or clock sources).
The mute bits may then be released after clocks have settled and the proper modes have been set.
It is required to have the device held in reset if the minimum high/low time specs of MCLK cannot be met
during clock source changes.
4.14
Control Port Interface
The Control Port is used to load all the internal register settings in order to operate in Software Mode (see
the
“Filter Plots” on page
42). The operation of the Control Port may be completely asynchronous with the
audio sample rate. However, to avoid potential interference problems, the Control Port pins should remain
static if no operation is required.
The Control Port operates in one of two modes: I²C or SPI.
4.14.1 MAP Auto Increment
The device has MAP (memory address pointer) auto-increment capability enabled by the INCR bit (also
the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads and
SPI writes. If INCR is set to 1, MAP will auto increment after each byte is written, allowing block reads or
writes of successive registers.
4.14.2 I²C Mode
In the I²C Mode, data is clocked into and out of the bi-directional serial control data line, SDA, by the serial
Control Port clock, SCL (see
enables the user to alter the chip address (001100[AD0][R/W]) and should be tied to VLC or GND, as re-
quired, before powering up the device. If the device ever detects a high-to-low transition on the AD0/CS
pin after power-up, SPI Mode will be selected.
4.14.2.1 I²C Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in
Section
2.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 0. The eighth
bit of the address byte is the R/W bit.
2. Wait for an acknowledge (ACK) from the part; then write to the memory address pointer, MAP. This
byte points to the register to be written.
3. Wait for an acknowledge (ACK) from the part; then write the desired data to the register pointed to by
the MAP.
4. If the INCR bit (see
Section
are written, then initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C writes to other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from step 1. If no further writes to other
registers are desired, initiate a STOP condition to the bus.
DS618F2
Figure 18
for the clock to data relationship). There is no CS pin. Pin AD0
4.14.1) is set to 1, repeat the previous step until all the desired registers
CS4382A
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