IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part NumberCS4382A-CQZ
DescriptionIC DAC 8CH 114DB 192KHZ 48LQFP
ManufacturerCirrus Logic Inc
CS4382A-CQZ datasheets
 

Specifications of CS4382A-CQZ

Package / Case48-LQFPNumber Of Bits24
Data InterfaceSerialNumber Of Converters8
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)680mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Conversion Rate192 KSPSResolution24 bit
Interface TypeSerialOperating Supply Voltage5 V
Operating Temperature Range+ 85 CMaximum Power Dissipation390 mW
Mounting StyleSMD/SMTNumber Of Dac Outputs8
Lead Free Status / RoHS StatusLead free / RoHS CompliantFor Use With598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time-Other names598-1061
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4.14.2.2 I²C Read
To read from the device, follow the procedure below while adhering to the Control Port Switching Speci-
fications.
1. Initiate a START condition to the I²C bus followed by the address byte. The upper 6 bits must be
001100. The seventh bit must match the setting of the AD0 pin, and the eighth must be 1. The eighth
bit of the address byte is the R/W bit.
2. After transmitting an acknowledge (ACK), the device will then transmit the contents of the register
pointed to by the MAP. The MAP register will contain the address of the last register written to the
MAP, or the default address (see
device.
3. Once the device has transmitted the contents of the register pointed to by the MAP, issue an ACK.
4. If the INCR bit is set to 1, the device will continue to transmit the contents of successive registers. Con-
tinue providing a clock and issue an ACK after each byte until all the desired registers are read; then
initiate a STOP condition to the bus.
5. If the INCR bit is set to 0 and further I²C reads from other registers are desired, it is necessary to initiate
a repeated START condition and follow the procedure detailed from steps 1 and 2 from the I²C Write
instructions followed by step 1 of the I²C Read section. If no further reads from other registers are de-
sired, initiate a STOP condition to the bus.
S D A
0 01 1 00
S C L
S ta rt
N o te : If o p e ra tio n is a w rite , th is b y te c o n ta in s th e M e m o ry A d d re s s P o in te r, M A P .
4.14.3 SPI Mode
In SPI Mode, data is clocked into the serial control data line, CDIN, by the serial Control Port clock, CCLK
(see
Figure 19
for the clock-to-data relationship). There is no AD0 pin. Pin CS is the chip select signal and
is used to control SPI writes to the Control Port. When the device detects a high-to-low transition on the
AD0/CS pin after power-up, SPI Mode will be selected. All signals are inputs and data is clocked in on the
rising edge of CCLK.
4.14.3.1 SPI Write
To write to the device, follow the procedure below while adhering to the Control Port Switching Specifica-
tions in
Section
2.
1. Bring CS low.
2. The address byte on the CDIN pin must then be 00110000.
3. Write to the memory address pointer, MAP. This byte points to the register to be written.
4. Write the desired data to the register pointed to by the MAP.
5. If the INCR bit (see
Section
are written, then bring CS high.
30
Section
4.14.1) if an I²C read is the first operation performed on the
N o te 1
A D D R
D AT A
R /W
A C K
A C K
AD 0
1-8
Figure 18. Control Port Timing, I²C Mode
4.14.1) is set to 1, repeat the previous step until all the desired registers
CS4382A
D A TA
A C K
1-8
S top
DS618F2