CS4382A-CQZ Cirrus Logic Inc, CS4382A-CQZ Datasheet - Page 34

IC DAC 8CH 114DB 192KHZ 48LQFP

CS4382A-CQZ

Manufacturer Part Number
CS4382A-CQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheets

Specifications of CS4382A-CQZ

Package / Case
48-LQFP
Number Of Bits
24
Data Interface
Serial
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
680mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Conversion Rate
192 KSPS
Resolution
24 bit
Interface Type
Serial
Operating Supply Voltage
5 V
Operating Temperature Range
+ 85 C
Maximum Power Dissipation
390 mW
Mounting Style
SMD/SMT
Number Of Dac Outputs
8
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1524 - BOARD EVAL FOR CS4382A DAC
Settling Time
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
598-1061

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
CS4382A-CQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
Part Number:
CS4382A-CQZ
Manufacturer:
CRIIUS
Quantity:
20 000
Part Number:
CS4382A-CQZR
Manufacturer:
Cirrus Logic Inc
Quantity:
10 000
34
6.1.5
6.2
6.2.1
DIF2
Reserved
0
0
0
0
1
1
1
1
7
0
Mode Control 2 (Address 02h)
Power Down (PDN)
Default = 1
0 - Disabled
1 - Enabled
Function:
The entire device will enter a low-power state when this function is enabled, and the contents of the control
registers are retained in this mode. The power-down bit defaults to ‘enabled’ on power-up and must be
disabled before normal operation in Control Port Mode can occur.
Digital Interface Format (DIF)
Default = 000 - Format 0 (Left-Justified, up to 24-bit data)
Function:
These bits select the interface format for the serial audio input. The Functional Mode bits determine
whether PCM or DSD Mode is selected.
PCM Mode: The required relationship between the Left/Right clock, serial clock and serial data is defined
by the Digital Interface Format and the options are detailed in
Note:
to ensure proper switching from one mode to another.
DIF1
0
0
1
1
0
0
1
1
While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set
DIF2
6
0
DIF0
0
1
0
1
0
1
0
1
Left-Justified, up to 24-bit data
I²S, up to 24-bit data
Right-Justified, 16-bit data
Right-Justified, 24-bit data
Right-Justified, 20-bit data
Right-Justified, 18-bit data
Reserved
Reserved
Table 5. Digital Interface Formats - PCM Mode
DIF1
5
0
DESCRIPTION
DIF0
4
0
Reserved
3
0
Figures
Reserved
2
0
7-12.
Format
2
3
4
5
0
1
-
-
Reserved
1
0
FIGURE
10
11
12
7
8
9
CS4382A
Reserved
DS618F2
0
0

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