AD1854JRSZ Analog Devices Inc, AD1854JRSZ Datasheet
AD1854JRSZ
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AD1854JRSZ Summary of contents
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FEATURES 5 V Stereo Audio DAC System Accepts 16-/18-/20-/24-Bit Data Supports 24 Bits and 96 kHz Sample Rate Multibit Sigma-Delta Modulator with “Perfect Differential Linearity Restoration” for Reduced Idle Tones and Noise Floor Data Directed Scrambling DAC—Least Sensitive to ...
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AD1854–SPECIFICATIONS TEST CONDITIONS UNLESS OTHERWISE NOTED Supply Voltages ( 5 Ambient Temperature 25°C 12.288 MHz (256 × F Input Clock Input Signal 1.0013 kHz –0.5 dB Full Scale Input Sample Rate 48 kHz Measurement ...
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POWER Supplies Voltage, Analog and Digital Analog Current Analog Current—Power-Down Digital Current Digital Current—Power-Down Dissipation Operation—Both Supplies Operation—Analog Supply Operation—Digital Supply Power-Down—Both Supplies Power Supply Rejection Ratio 1 kHz 300 mV p-p Signal at Analog Supply Pins 20 kHz 300 ...
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AD1854 ABSOLUTE MAXIMUM RATINGS* Min DV to DGND –0 AGND –0.3 DD Digital Inputs DGND – 0.3 Analog Outputs AGND – 0.3 AGND to DGND –0.3 Reference Voltage Soldering *Stresses greater than those listed under Absolute Maximum ...
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Pin Input/Output Pin Name 1 I DGND 2 I MCLK 3 I CLATCH 4 I CCLK 5 I CDATA 6 I 384/256 7 I X2MCLK 8 O ZEROR 9 I DEEMP 10 I 96/48 11 AGND 12 O ...
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AD1854 OPERATING FEATURES Serial Data Input Port The AD1854’s flexible serial data input port accepts data in twos-complement, MSB-first format. The left channel data field always precedes the right channel data field. The input data consists of either 16, 18, ...
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L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA MSB MSB–1 MSB–2 INPUT L/RCLK LEFT CHANNEL INPUT BCLK INPUT SDATA LSB MSB MSB–1 MSB–2 INPUT t CCP CDATA D15 CCLK t CCH t CCL CLATCH Serial Control Port The AD1854 serial control ...
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AD1854 CLATCH CCLK CDATA 20 40 CLATCH CCLK CDATA 200 400 Burst Mode To operate with SPI CCLK frequencies up to 12.288 MHz, the SPI port can be operated in Burst Mode. This means that when CLATCH is high, CCLK ...
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Timing Diagrams The serial data port timing is shown in Figures 9 and 10. The minimum bit clock HI pulsewidth is t DBH clock LO pulsewidth The minimum bit clock period is DBL t . The left/right ...
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AD1854 SELECT RATE X2MCLK 384/256 96/48 DVDD SPDIF DIRECT DIRECT MCLK/ SEL 10k 10k 10k JP1 SDATA LRCLK AUDIO SCLK DATA MCLK I/F MODE IDPM1 IDPM0 RJ, 16-BIT RJ, 20-BIT ...
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TYPICAL PERFORMANCE Figures 13 through 20 illustrate the typical analog performance of the AD1854 as measured by an Audio Precision System Two. Signal-to-Noise and THD+N performance are shown under a range of conditions. Figure 14 shows the power supply rejection ...
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AD1854 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 100 FREQUENCY – kHz Figure 19. Digital Filter Response 0.32 (8.20) 0.29 (7.40) 0.079 (2.0) MAX (0.05) 0 –10 –20 –30 –40 –50 ...