AD5541ARZ Analog Devices Inc, AD5541ARZ Datasheet - Page 12

IC DAC 16BIT SERIAL IN 8-SOIC

AD5541ARZ

Manufacturer Part Number
AD5541ARZ
Description
IC DAC 16BIT SERIAL IN 8-SOIC
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD5541ARZ

Data Interface
DSP, MICROWIRE™, QSPI™, Serial, SPI™
Design Resources
How to Achieve High Precision Voltage Level Setting Using AD5541A/42A (CN0169)
Settling Time
1µs
Number Of Bits
16
Number Of Converters
1
Voltage Supply Source
Single Supply
Power Dissipation (max)
6.05mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Resolution (bits)
16bit
Sampling Rate
1.5MSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
2.7V To 5.5V
Supply Current
300µA
Digital Ic Case Style
SOIC
Number Of Channels
1
Resolution
16b
Interface Type
SER 3W SPI QSPI UW
Single Supply Voltage (typ)
5V
Dual Supply Voltage (typ)
Not RequiredV
Architecture
R-2R
Power Supply Requirement
Single
Output Type
Voltage
Single Supply Voltage (min)
4.5V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
8
Package Type
SOIC N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

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AD5541/AD5542
Assuming a perfect reference, the unipolar worst-case output
voltage can be calculated from the following equation:
where:
V
D is code loaded to DAC.
V
V
V
INL is integral nonlinearity in volts.
BIPOLAR OUTPUT OPERATION
With the aid of an external op amp, the AD5542 can be confi-
gured to provide a bipolar voltage output. A typical circuit of
such operation is shown in Figure 24. The matched bipolar
offset resistors, R
amp to achieve this bipolar output swing, typically R
28 kΩ. Table 8 shows the transfer function for this output
operating mode. Also provided on the AD5542 are a set of
Kelvin connections to the analog ground inputs.
Table 8. Bipolar Code Table
DAC Latch Contents
MSB
1111 1111 1111 1111
1000 0000 0000 0001
1000 0000 0000 0000
0111 1111 1111 1111
0000 0000 0000 0000
OUT−UNI
REF
GE
ZSE
is gain error in volts.
is reference voltage applied to the part.
is zero scale error in volts.
V
INTERFACE
SERIAL
OUT-UNI
is unipolar mode worst-case output.
=
0.1µF
Figure 24. Bipolar Output (AD5542 Only)
CS
DIN
SCLK
LDAC
2
D
FB
16
V
LSB
DGND AGNDF
+5V
DD
and R
×
(
V
+2.5V
AD5541/AD5542
REF
REFF
INV
0.1µF
+
, are connected to an external op
Analog Output
+V
+V
0 V
−V
−V
V
10µF
REFS
REF
REF
REF
REF
AGNDS
GE
R
× (32,767/32,768)
× (1/32,768)
× (1/32,768)
× (32,768/32,768) = −V
INV
)
+
V
RFB
R
ZSE
FB
OUT
+
INV
INL
EXTERNAL
OP AMP
+5V
–5V
FB
= R
UNIPOLAR
REF
OUTPUT
INV
Rev. E | Page 12 of 20
=
Assuming a perfect reference, the worst-case bipolar output
voltage can be calculated from the following equation:
where:
V
V
V
RD is the R
A is the op amp open-loop gain.
OUTPUT AMPLIFIER SELECTION
For bipolar mode, a precision amplifier should be used and
supplied from a dual power supply. This provides the ±V
output. In a single-supply application, selection of a suitable op
amp may be more difficult as the output swing of the amplifier
does not usually include the negative rail, in this case, AGND.
This can result in some degradation of the specified performance
unless the application does not use codes near zero.
The selected op amp needs to have a very low-offset voltage (the
DAC LSB is 38 μV with a 2.5 V reference) to eliminate the need
for output offset trims. Input bias current should also be very
low because the bias current, multiplied by the DAC output
impedance (approximately 6 kΩ), adds to the zero code error.
Rail-to-rail input and output performance is required. For fast
settling, the slew rate of the op amp should not impede the
settling time of the DAC. Output impedance of the DAC is
constant and code-independent, but to minimize gain errors,
the input impedance of the output amplifier should be as high
as possible. The amplifier should also have a 3 dB bandwidth of
1 MHz or greater. The amplifier adds another time constant to
the system, hence increasing the settling time of the output. A
higher 3 dB amplifier bandwidth results in a shorter effective
settling time of the combined DAC and amplifier.
FORCE SENSE AMPLIFIER SELECTION
Use single-supply, low-noise amplifiers. A low-output impedance
at high frequencies is preferred because the amplifiers need to
be able to handle dynamic currents of up to ±20 mA.
REFERENCE AND GROUND
Because the input impedance is code-dependent, the reference
pin should be driven from a low impedance source. The AD5541/
AD5542 operate with a voltage reference ranging from 2 V to
V
scale output voltage of the DAC is determined by the reference.
Table 7 and Table 8 outline the analog output voltage or partic-
ular digital codes. For optimum performance, Kelvin sense
connections are provided on the AD5542.
If the application does not require separate force and sense
lines, tie the lines close to the package to minimize voltage
drops between the package leads and the internal die.
OUT-BIP
OUT−UNI
OS
DD
is the external op amp input offset voltage.
. References below 2 V result in reduced accuracy. The full-
V
OUT-BIP
is the bipolar mode worst-case output.
is the unipolar mode worst-case output.
FB
=
and R
[
(
V
OUT
INV
resistor matching error.
UNI
+
V
1
OS
+
)
(
(
2
2
+
+
RD
RD
)
)
A
V
REF
(
1
+
RD
)
REF
]

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