CONV D/A 12BIT MICRO PWR TSOT236

DAC121S101CIMK/NOPB

Manufacturer Part NumberDAC121S101CIMK/NOPB
DescriptionCONV D/A 12BIT MICRO PWR TSOT236
ManufacturerNational Semiconductor
SeriesPowerWise®
DAC121S101CIMK/NOPB datasheet
 


Specifications of DAC121S101CIMK/NOPB

Settling Time12µsNumber Of Bits12
Data InterfaceDSP, MICROWIRE™, QSPI™, Serial, SPI™Number Of Converters1
Voltage Supply SourceSingle SupplyPower Dissipation (max)1.72mW
Operating Temperature-40°C ~ 105°CMounting TypeSurface Mount
Package / CaseTSOT-23-6, TSOT-6Number Of Channels1
Resolution12bInterface TypeSerial (3-Wire, SPI, QSPI, Microwire)
Single Supply Voltage (typ)3.3/5VDual Supply Voltage (typ)Not RequiredV
ArchitectureResistor-StringPower Supply RequirementSingle
Output TypeVoltageIntegral Nonlinearity Error±8LSB
Single Supply Voltage (min)2.7VSingle Supply Voltage (max)5.5V
Dual Supply Voltage (min)Not RequiredVDual Supply Voltage (max)Not RequiredV
Operating Temp Range-40C to 105COperating Temperature ClassificationIndustrial
MountingSurface MountPin Count6
Package TypeTSOTFor Use WithDAC121S101EVAL - BOARD EVALUATION DAC121S101
Lead Free Status / RoHS StatusLead free / RoHS CompliantOther namesDAC121S101CIMK
DAC121S101CIMKTR
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1.0 Functional Description
1.1 DAC SECTION
The DAC121S101 is fabricated on a CMOS process with an
architecture that consists of switches and a resistor string that
are followed by an output buffer. The power supply serves as
the reference voltage. The input coding is straight binary with
an ideal output voltage of:
V
= V
x (D / 4096)
OUT
A
where D is the decimal equivalent of the binary code that is
loaded into the DAC register and can take on any value be-
tween 0 and 4095.
1.2 RESISTOR STRING
The resistor string is shown in
Figure
of 4096 equal valued resistors with a switch at each junction
of two resistors, plus a switch to ground. The code loaded into
the DAC register determines which switch is closed, connect-
ing the proper node to the amplifier. This configuration guar-
antees that the DAC is monotonic.
FIGURE 3. DAC Resistor String
Normally, the SYNC line is kept low for at least 16 falling
edges of SCLK and the DAC is updated on the 16th SCLK
falling edge. However, if SYNC is brought high before the 16th
falling edge, the shift register is reset and the write sequence
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1.3 OUTPUT AMPLIFIER
The output buffer amplifier is a rail-to-rail type, providing an
output voltage range of 0V to V
rail types, exhibit a loss of linearity as the output approaches
the supply rails (0V and V
linearity is specified over less than the full output range of the
DAC. The output capabilities of the amplifier are described in
the Electrical Tables.
1.4 SERIAL INTERFACE
The three-wire interface is compatible with SPI, QSPI and
MICROWIRE, as well as most DSPs. See the Timing Diagram
for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once
SYNC is low, the data on the D
3. This string consists
bit serial input register on the falling edges of SCLK. On the
16th falling clock edge, the last data bit is clocked in and the
programmed function (a change in the mode of operation and/
or a change in the DAC register contents) is executed. At this
point the SYNC line may be kept low or brought high. In either
case, it must be brought high for the minimum specified time
before the next write sequence as a falling edge of SYNC can
initiate the next write cycle.
Since the SYNC and D
are high, they should be idled low between write sequences
to minimize power consumption.
1.5 INPUT SHIFT REGISTER
The input shift register,
two bits are "don't cares" and are followed by two bits that
determine the mode of operation (normal mode or one of
three power-down modes). The contents of the serial input
register are transferred to the DAC register on the sixteenth
falling edge of SCLK. See Timing Diagram,
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FIGURE 4. Input Register Contents
is invalid. The DAC register is not updated and there is no
change in the mode of operation or in the output voltage.
14
. All amplifiers, even rail-to-
A
, in this case). For this reason,
A
line is clocked into the 16-
IN
buffers draw more current when they
IN
Figure
4, has sixteen bits. The first
Figure
2.
20114908