DAC121C081CISD/NOPB National Semiconductor, DAC121C081CISD/NOPB Datasheet - Page 16

• Manufacturer Part Number: DAC121C081CISD/NOPB
• Description: IC DAC 12BIT MICROPWR I2C 6-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DAC121C081CISD/NOPB

• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: I²C
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 730µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 6-LLP
• For Use With: DAC121C08XEB - BOARD EVAL FOR DAC121C081/5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DAC121C081CISD; DAC121C081CISD; DAC121C081CISDTR

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1.4.3 High-Speed (Hs) Mode
For Hs-mode, the sequence of events to begin communica-
tion differ slightly from Standard-Fast mode. Figure 5 de-
scribes this in further detail. Initially, the bus begins running
in Standard-Fast mode. The master generates a Start condi-
tion and sends the 8-bit Hs master code (00001XXX) to the
DAC121C081. Next, the DAC121C081 responds with a
NACK. Once the SCL line has been pulled to a high level, the
master switches to Hs-mode by increasing the bus speed and
generating a Repeated Start condition (driving SDA low while
SCL is pulled high). At this point, the master sends the slave
1.4.4 I
The DAC has a seven-bit I
version of the DAC, this address is configured by the ADR0
and ADR1 address selection inputs. For the DAC121C081,
the address is configured by the ADR0 address selection in-
put. ADR0 and ADR1 can be grounded, left floating, or tied to
V
2 rather than left floating. The state of these inputs sets the
address the DAC responds to on the I
In addition to the selectable slave address, there is also a
broadcast address (1001000) for all DAC121C081's and
* Pin-compatible alternatives to the DAC121C081 options are available with additional address options.
A
. If desired, the address selection inputs can be set to V
2
C Slave (Hardware) Address
Slave Address
2
C slave address. For the MSOP-8
[A6 - A0]
0001100
0001101
0001110
0001000
0001001
0001010
1001100
1001101
1001110
1001000
2
FIGURE 5. Beginning Hs-Mode Communication
C bus (see Table 1).
TABLE 1. Slave Addresses
Floating
Floating
Floating
ADR1
GND
GND
GND
DAC121C085 (MSOP-8)
V
V
V
--------------- Broadcast Address ---------------
A
A
A
A
/
16
address to the DAC121C081, and communication continues
as shown above in the "Basic Operation" Diagram (see Figure
4).
When the master generates a Repeated Start condition while
in Hs-mode, the bus stays in Hs-mode awaiting the slave ad-
dress from the master. The bus continues to run in Hs-mode
until a Stop condition is generated by the master. When the
master generates a Stop condition on the bus, the bus must
be started in Standard-Fast mode again before increasing the
bus speed and switching to Hs-mode. ns16705
DAC121C085's on the 2-wire bus. When the bus is addressed
by the broadcast address, all the DAC121C081's and
DAC121C085's will respond and update synchronously. Fig-
ure 6 and Figure 7 describe how the master device should
address the DAC via the I
Keep in mind that the address selection inputs (ADR0 and
ADR1) are only sampled until the DAC is correctly addressed
with a non-broadcast address. At this point, the ADR0 and
ADR1 inputs TRI-STATE and the slave address is "locked".
Changes to ADR0 and ADR1 will not update the selected
slave address until the device is power-cycled.
Floating
Floating
Floating
ADR0
GND
GND
GND
V
V
V
A
A
A
(TSOT & LLP) *
DAC121C081
---------------
---------------
---------------
---------------
---------------
---------------
Floating
ADR0
2
GND
C-Compatible interface.
V
A
30004912