DAC124S085CIMM/NOPB National Semiconductor, DAC124S085CIMM/NOPB Datasheet - Page 3

• Manufacturer Part Number: DAC124S085CIMM/NOPB
• Description: IC DAC 12BIT QUAD R-R 10-MSOP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DAC124S085CIMM/NOPB

• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: DSP, MICROWIRE™, QSPI™, Serial, SPI™
• Number Of Converters: 4
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 105°C
• Mounting Type: Surface Mount
• Package / Case: 10-MSOP, Micro10™, 10-uMAX, 10-uSOP
• Number Of Channels: 4
• Resolution: 12b
• Interface Type: Serial (3-Wire, SPI, QSPI, Microwire)
• Single Supply Voltage (typ): 3.3/5V
• Dual Supply Voltage (typ): Not RequiredV
• Architecture: Resistor-String
• Power Supply Requirement: Single
• Output Type: Voltage
• Integral Nonlinearity Error: ±8LSB
• Single Supply Voltage (min): 2.7V
• Single Supply Voltage (max): 5.5V
• Dual Supply Voltage (min): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Operating Temp Range: -40C to 105C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 10
• Package Type: MSOP
• For Use With: DAC124S085EB - BOARD EVALUATION DAC124S085
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Power Dissipation (max): -
• Lead Free Status / Rohs Status: Compliant
• Other names: DAC124S085CIMM; DAC124S085CIMMTR

Pin Descriptions
Pin No.
MSOP
LLP
10
11
1
2
3
4
5
6
7
8
9
(LLP only)
Symbol
V
SYNC
V
V
V
V
SCLK
GND
PAD
OUTC
OUTD
REFIN
D
OUTA
OUTB
V
IN
A
Analog Output
Analog Output
Analog Output
Analog Output
Analog Input
Digital Input
Digital Input
Digital Input
Ground
Ground
Supply
Type
Power supply input. Must be decoupled to GND.
Channel A Analog Output Voltage.
Channel B Analog Output Voltage.
Channel C Analog Output Voltage.
Channel D Analog Output Voltage.
Ground reference for all on-chip circuitry.
Unbuffered reference voltage shared by all channels. Must be decoupled
to GND.
Serial Data Input. Data is clocked into the 16-bit shift register on the falling
edges of SCLK after the fall of SYNC.
Frame synchronization input for the data input. When this pin goes low,
it enables the input shift register and data is transferred on the falling
edges of SCLK. The DAC is updated on the 16th clock cycle unless
SYNC is brought high before the 16th clock, in which case the rising edge
of SYNC acts as an interrupt and the write sequence is ignored by the
DAC.
Serial Clock Input. Data is clocked into the input shift register on the
falling edges of this pin.
Exposed die attach pad can be connected to ground or left floating.
Soldering the pad to the PCB offers optimal thermal performance and
enhances package self-alignment during reflow.
3
Description
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