DAC108S085CIMT/NOPB National Semiconductor, DAC108S085CIMT/NOPB Datasheet - Page 16

IC DAC 10BIT OCTAL R-R 16-TSSOP

DAC108S085CIMT/NOPB

Manufacturer Part Number
DAC108S085CIMT/NOPB
Description
IC DAC 10BIT OCTAL R-R 16-TSSOP
Manufacturer
National Semiconductor
Series
PowerWise®r
Datasheet

Specifications of DAC108S085CIMT/NOPB

Settling Time
4.5µs
Number Of Bits
10
Data Interface
Serial
Number Of Converters
8
Voltage Supply Source
Single Supply
Power Dissipation (max)
4.85mW
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Package / Case
16-TSSOP
For Use With
DAC108S085EB - BOARD EVALUATION FOR DAC108S085
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DAC108S085CIMT

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1.7 POWER-ON RESET
The power-on reset circuit controls the output voltages of the
eight DACs during power-up. Upon application of power, the
DAC registers are filled with zeros and the output voltages are
set to 0V. The outputs remain at 0V until a valid write se-
quence is made.
1.8 POWER-DOWN MODES
The DAC108S085 has three power-down modes where dif-
ferent output terminations can be selected (see Table 4). With
all channels powered down, the supply current drops to 0.1
µA at 3V and 0.2 µA at 5V. By selecting the channels to be
powered down in DB[7:0] with a "1", individual channels can
be powered down separately or multiple channels can be
powered down simultaneously. The three different output ter-
2.0 Applications Information
2.1 EXAMPLES PROGRAMMING THE DAC108S085
This section will present the step-by-step instructions for pro-
gramming the serial input register.
2.1.1 Updating DAC Outputs Simultaneously
When the DAC108S085 is first powered on, the DAC is op-
erating in Write Register Mode (WRM). Operating in WRM
allows the user to program the registers of multiple DAC
channels without causing the DAC outputs to be updated. As
an example, here are the steps for setting Channel A to a full
scale output, Channel B to three-quarters full scale, Channel
C to half-scale, Channel D to one-quarter full scale and having
all the DAC outputs update simultaneously.
As stated previously, the DAC108S085 powers up in WRM.
If the device was previously operating in Write Through Mode
(WTM), an extra step to set the DAC into WRM would be re-
quired. First, the DAC registers need to be programmed to the
desired values. To set Channel A to an output of full scale,
write "0FFC" to the control register. This will update the data
register for Channel A without updating the output of Channel
A. Second, set Channel B to an output of three-quarters full
scale by writing "1C00" to the control register. This will update
the data register for Channel B. Once again, the output of
Channel B and Channel A will not be updated since the DAC
is operating in WRM. Third, set Channel C to half scale by
writing "2800" to the control register. Fourth, set Channel D
to one-quarter full scale by writing "3400" to the control reg-
ister. Finally, update all four DAC channels simultaneously by
writing "A00F" to the control register. This procedure allows
the user to update four channels simultaneously with five
steps.
Since Channel A was one of the DACs to be updated, one
command step could have been saved by writing to Channel
A last. This is accomplished by writing to Channel B, C, and
D first and using the the special command "Channel A Write"
DB[15:12]
1 1 0 1
1 1 1 0
1 1 1 1
DB[11:8]
X X X X
X X X X
X X X X
H
H
H
7
TABLE 4. Power-Down Modes
G
G
G
6
 5
F
F
F
E
E
E
4
16
minations include high output impedance, 100k ohm to
ground, and 2.5k ohm to ground.
The output amplifiers, resistor strings, and other linear cir-
cuitry are all shut down in any of the power-down modes. The
bias generator, however, is only shut down if all the channels
are placed in power-down mode. The contents of the DAC
registers are unaffected when in power-down. Therefore,
each DAC register maintains its value prior to the
DAC108S085 being powered down unless it is changed dur-
ing the write sequence which instructed it to recover from
power down. Minimum power consumption is achieved in the
power-down mode with SYNC idled high, D
SCLK disabled. The time to exit power-down (Wake-Up Time)
is typically 3 µsec at 3V and 20 µsec at 5V.
to update Channel A's DAC register and output. This special
command has the added benefit of updating all DAC outputs
while updating Channel A. With this sequence of commands,
the user was able to update four channels simultaneously with
four steps. A summary of this command can be found in Table
3.
2.1.2 Updating DAC Outputs Independently
If the DAC108S085 is currently operating in WRM, change
the mode of operation to WTM by writing "9XXX" to the control
register. Once the DAC is operating in WTM, any DAC chan-
nel can be updated in one step. For example, if a design
required Channel G to be set to half scale, the user can write
"6800" to the control register and Channel G's data register
and DAC output will be updated. Similarly, if Channel F's out-
put needed to be set to full scale, "5FFC" would need to be
written to the control register. Channel A is the only channel
that has a special command that allows its DAC output to be
updated in one command regardless of the mode of opera-
tion. Setting Channel A's DAC output to full scale could be
accomplished in one step by writing "BFFF" to the control
register.
2.2 USING REFERENCES AS POWER SUPPLIES
While the simplicity of the DAC108S085 implies ease of use,
it is important to recognize that the path from the reference
input (V
ply Rejection Ratio (PSRR). Therefore, it is necessary to
provide a noise-free supply voltage to V
lize the full dynamic range of the DAC108S085, the supply
pin (V
same supply voltage. Since the DAC108S085 consumes very
little power, a reference source may be used as the reference
input and/or the supply voltage. The advantages of using a
reference source over a voltage regulator are accuracy and
stability. Some low noise regulators can also be used. Listed
below are a few reference and power supply options for the
DAC108S085.
D
D
D
3
A
C
C
C
2
) and V
REF1,2
B
B
B
1
) to the DAC outputs will have zero Power Sup-
REF1,2
0
A
A
A
can be connected together and share the
Output Impedance
100 kΩ outputs
High-Z outputs
2.5 kΩ outputs
REF1,2
IN
. In order to uti-
idled low, and

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