IC 20-BIT MONOLITHIC D/A 16-QSOP

DAC1220E

Manufacturer Part NumberDAC1220E
DescriptionIC 20-BIT MONOLITHIC D/A 16-QSOP
ManufacturerTexas Instruments
DAC1220E datasheet
 


Specifications of DAC1220E

Settling Time1.8msNumber Of Bits20
Data InterfaceSerialNumber Of Converters1
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)3.5mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case16-QSOPResolution20 bit
Interface TypeSerial (2-Wire, 3-Wire, SPI)Supply Voltage (max)5.25 V
Supply Voltage (min)4.75 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
For Use With296-17265 - MODULE EVALUATION FOR DAC1220Lead Free Status / RoHS StatusLead free / RoHS Compliant
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The chip-select pin CS is active low. When CS is
high, activity on SCLK is ignored. There are certain
timing limits and delays which apply to the
manipulation of CS, as shown in
must be observed, or the DAC1220 may malfunction.
If CS is not used, it should be tied low. When CS is
tied low, different timing limits and delays must be
observed, as shown in
Figure
9. If these are violated,
the DAC1220 may malfunction.
The serial interface is byte-oriented. All data is
transferred in groups of eight bits.
I/O Recovery
The DAC1220 has a timeout on the serial interface. If
f
is 2.5MHz, the timeout is approximately 100ms.
CLK
At 2.5MHz, if a command is interrupted, and no
activity occurs on the SCLK or CS lines for 100ms,
the DAC1220 will cancel the command. If the
command was a write command, no registers are
affected.
The timeout period scales with the frequency of f
SCLK
SYMBOL
DESCRIPTION
t
First high period
16
t
Low period
17
t
Second high period
18
t
Third high period
19
Copyright © 1998–2009, Texas Instruments Incorporated
SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009
SCLK Reset Pattern
The DAC1220 does not have a dedicated reset pin.
Instead, it contains a circuit which waits for a special
Figure
10. These
pattern to appear on SCLK, and triggers the internal
hardware reset line when it detects the special
pattern.
This pattern, called the SCLK reset pattern, is shown
in
Figure
12, with timing information given in
The pattern is very different from the usual clocking
patterns which appear on SCLK, and is unlikely to be
detected by accident during normal operation.
The SCLK reset pattern can only be triggered when
CS is low. When CS is high, the SCLK line is ignored,
and the SCLK reset pattern is not detected.
.
CLK
t
t
17
17
t
t
t
16
18
19
Figure 12. Resetting the DAC1220
Table 5. Reset Timing Characteristics
MIN
512 × t
XIN
10 × t
XIN
1024 × t
XIN
2048 × t
XIN
Product Folder Link(s):
DAC1220
DAC1220
Table
5.
Reset On
Falling Edge
NOM
MAX
UNITS
800 × t
ns
XIN
ns
1800 × t
ns
XIN
2400 × t
ns
XIN
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