IC 20-BIT MONOLITHIC D/A 16-QSOP

DAC1220E

Manufacturer Part NumberDAC1220E
DescriptionIC 20-BIT MONOLITHIC D/A 16-QSOP
ManufacturerTexas Instruments
DAC1220E datasheet
 


Specifications of DAC1220E

Settling Time1.8msNumber Of Bits20
Data InterfaceSerialNumber Of Converters1
Voltage Supply SourceAnalog and DigitalPower Dissipation (max)3.5mW
Operating Temperature-40°C ~ 85°CMounting TypeSurface Mount
Package / Case16-QSOPResolution20 bit
Interface TypeSerial (2-Wire, 3-Wire, SPI)Supply Voltage (max)5.25 V
Supply Voltage (min)4.75 VMaximum Operating Temperature+ 85 C
Mounting StyleSMD/SMTMinimum Operating Temperature- 40 C
For Use With296-17265 - MODULE EVALUATION FOR DAC1220Lead Free Status / RoHS StatusLead free / RoHS Compliant
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Fast Settling Mode
To speed up settling, the DAC1220 can change the
cutoff frequency of its output filter. Raising the cutoff
frequency causes the DAC1220 to settle faster, but at
the expense of higher noise. The adaptive filtering
mode provides a good compromise by increasing the
filter frequency only while the DAC is changing its
output by more than approximately 40mV. When the
output has settled, the filter frequency is reduced
again.
Adaptive filtering is controlled by the ADPT and DISF
bits in the Command Register. The action of these
bits together is described in
Table
10.
Table 10. Fast Settling Modes
ADPT
DISF
(CMR bit 15)
(CMR bit 4)
FAST SETTLING MODE
0
0
Fast settling only during > 40mV
step
0
1
Disabled
1
0
Fast settling always on (filter cutoff
increased)
1
1
Disabled
space
Command Register (CMR)
The command register contains the configuration bits of the DAC1220. It is shown in
command register are shown in
Table
Writes to the CMR take effect at the negative edge of SCLK during the last bit of the last byte of the write
command.
blank
15
14
13
ADPT
CALPIN
Reserved
R/W-0
R/W-0
R-1
(1) In early versions of the DAC1220, this bit was rw-0. See the
7
6
5
RES
CLR
DF
R/W-0
R/W-0
R/W-0
LEGEND: R = Read, W = Write
Copyright © 1998–2009, Texas Instruments Incorporated
SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009
REGISTERS
The register map is shown in
Table 11. Register Memory Map
ADDRESS
13.
Table 12. Command Register
12
11
Reserved
Reserved
(1)
R-0
R-1
Calibration
section for details.
4
3
DISF
BD
R/W-0
R/W-0
Product Folder Link(s):
DAC1220
DAC1220
Table
11.
CONTENT
0
DIR byte 2 (MSB)
1
DIR byte 1
2
DIR byte 0 (LSB)
3
Reserved
4
CMR byte 1 (MSB)
5
CMR byte 0 (LSB)
6
Reserved
7
Reserved
8
OCR byte 2 (MSB)
9
OCR byte 1
10
OCR byte 0 (LSB)
11
Reserved
12
FCR byte 2 (MSB)
13
FCR byte 1
14
FCR byte 0 (LSB)
15
Reserved
Table
12. The bits in the
10
9
8
Reserved
CRST
Reserved
R-0
R/W-0
R-0
2
1
0
MSB
MD
R/W-0
R/W-10b
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