The output voltage range is nominally 0V to 2 × V
It does not go below ground. The output amplifier is
not designed for heavy loads; it can drive a maximum
of 0.5mA. At power-on and during sleep mode, the
amplifier is disconnected, so the output is high
The output is not fully linear to the rails; maximum
linearity is specified from (AGND + 20mV) to (AV
20mV). For linearity from 0–5V, AV
increased to 5.02V or more, and AGND can be
decreased to –20mV or less. As long as the specified
operating limits are observed, this will not damage
The continuous-time output filter requires two external
capacitors to operate. The recommended values of
these capacitors depend on whether the DAC1220
will be operated in 16-bit or 20-bit mode, and are
Table 1. Filter Capacitor Values
The capacitors should be stable and high grade. Film
types, or other capacitors designed for precision
filtering, are strongly recommended. Low-quality
capacitors will degrade performance significantly.
pins are very sensitive. It is critical to
surround them with a guard ring at the reference
voltage for best noise performance. See the
section for more information.
The voltage reference input is designed for +2.5V. At
this voltage, the output will range from ground to
approximately 5V, as noted above.
Copyright © 1998–2009, Texas Instruments Incorporated
SBAS082G – FEBRUARY 1998 – REVISED SEPTEMBER 2009
The digital lines, except for the crystal oscillator lines,
operate at TTL-compatible CMOS logic levels. They
can be driven from 3.3V logic sources.
In noise-sensitive applications, it may be helpful to
keep the level transition rates on the digital lines
slow. Fast transitions can couple through the device
to the output, causing noise. Rate limiting can be
done with resistance or even an RC filter.
The DAC1220 has a built-in crystal oscillator at pins
. To use it, connect a crystal and load
capacitors as shown in
12pF load capacitors are shown in the schematic, but
the correct value depends mainly on the crystal and
layout, and not on the oscillator itself. Load
frequency, and reliability. If startup is unreliable, try
lowering the capacitor values. Remember that
parasitic board and pin capacitance can be a
significant portion of the crystal load capacitance.
When the crystal oscillator is operating, a sinusoidal
signal of relatively low amplitude will be observed at
both the X
The typical frequency to use with the DAC1220 is
2.5MHz. Deviating too far from this may alter noise
and settling time, as well as timing characteristics.
Connecting an External Clock
An external clock signal can be connected at X
CMOS or TTL logic signal can be used. If an external
clock signal is used, X
In some cases, an RC filter on the clock line may
Product Folder Link(s):
should be left unconnected.
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