CS43L22-CNZ Cirrus Logic Inc, CS43L22-CNZ Datasheet
CS43L22-CNZ
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CS43L22-CNZ Summary of contents
Page 1
... Left Right Inputs Inputs Copyright Cirrus Logic, Inc. 2010 (All Rights Reserved) CS43L22 2 x 1.00 W into 8 Ω 550 mW into 8 Ω 230 mW into 8 Ω 1.90 W into 4 Ω 1.00 W into 4 Ω 350 mW into 4 Ω @ 2.5 V Battery Level Monitoring & Compensation Battery ...
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... The CS43L22 is available in a 40-pin QFN package in Com- mercial (-40 to +85 °C) grade. The CS43L22 Customer Demonstration board is also available for device evaluation and implementation suggestions. Please refer to formation” ...
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... Map Increment (INCR) ............................................................................................... 34 6. REGISTER QUICK REFERENCE ........................................................................................................ 35 7. REGISTER DESCRIPTION .................................................................................................................. 37 7.1 Chip I.D. and Revision Register (Address 01h) (Read Only) ......................................................... 37 7.1.1 Chip I.D. (Read Only) ............................................................................................................ 37 7.1.2 Chip Revision (Read Only) .................................................................................................... 37 7.2 Power Control 1 (Address 02h) ...................................................................................................... 37 DS792F2 Confidential Draft 3/4/10 CS43L22 3 ...
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... Passthrough x Volume: PASSAVOL (Address 14h) & PASSBVOL (Address 15h) .................... 46 7.13.1 Passthrough x Volume ........................................................................................................ 46 7.14 PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh) ................................................... 47 7.14.1 PCM Channel x Mute .......................................................................................................... 47 7.14.2 PCM Channel x Volume ...................................................................................................... 47 7.15 Beep Frequency & On Time (Address 1Ch) ................................................................................ 47 7.15.1 Beep Frequency .................................................................................................................. 47 7.15.2 Beep On Time ..................................................................................................................... 48 4 Confidential Draft 3/4/10 CS43L22 DS792F2 ...
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... Charge Pump Frequency .................................................................................................... 58 8. ANALOG PERFORMANCE PLOTS .................................................................................................... 59 8.1 Headphone THD+N versus Output Power Plots ............................................................................ 59 9. EXAMPLE SYSTEM CLOCK FREQUENCIES .................................................................................... 61 9.1 Auto Detect Enabled 9.2 Auto Detect Disabled ................................................................................................................... 61 10. PCB LAYOUT CONSIDERATIONS ................................................................................................... 62 10.1 Power Supply, Grounding ............................................................................................................ 62 10.2 QFN Thermal Pad ........................................................................................................................ 62 DS792F2 Confidential Draft 3/4/10 ................................................................................................................... 61 CS43L22 5 ...
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... Figure 19. THD+N vs. Output Power per Channel at 2.5 V (16 Ω load) ................................................... 59 Figure 20. THD+N vs. Output Power per Channel at 1.8 V (32 Ω load) ................................................... 60 Figure 21. THD+N vs. Output Power per Channel at 2.5 V (32 Ω load) ................................................... 60 Figure 22. Passband Ripple ...................................................................................................................... 63 Figure 23. Stopband .................................................................................................................................. 63 Figure 24. DAC Transition Band ............................................................................................................... 63 Figure 25. Transition Band (Detail) ........................................................................................................... 63 6 Confidential Draft 3/4/10 CS43L22 DS792F2 ...
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... Headphone/Line Audio Output (Output) - Stereo headphone or line level analog outputs Analog Power (Input) - Positive power for the internal analog section. DS792F2 Confidential Draft 3/4/ GND/Thermal Pad 25 24 Top-Down (Through-Package) View 40-Pin QFN Package Pin Description CS43L22 AIN1B AIN1A AFILTB AFILTA AIN2B AIN2A AIN3B AIN3A AIN4B AIN4A 7 ...
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... Weak Pull-up 1. 3.47 V, CMOS (~1 MΩ 1 5.25 V Power MOSFET - 1 5.25 V Power MOSFET - 1 5.25 V Power MOSFET - 1 5.25 V Power MOSFET CS43L22 Receiver 1. 3.47 V, with Hysteresis 1. 3.47 V, with Hysteresis 1. 3.47 V, with Hysteresis 1. 3.47 V, with Hysteresis 1. 3. 3. 3. 3. DS792F2 ...
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... AIN3A AIN3B AIN4A AIN4B AGND TSTO AFILTA TSTO AFILTB VQ FILT+ DGND Figure 1. Typical Connection Diagram CS43L22 +1 +2.5 V 0.1 µF 1 µF See Note 4 Line Level Out 47 kΩ Left & Right 0.022 µF 51.1 Ω Headphone Out Left & Right 51.1 Ω ...
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... Confidential Draft 3/4/10 Commercial Symbol Analog VA, VHP Speaker VP Digital VD Serial/Control Port Interface VL (Note (Note (Note (Note 2) V IND stg CS43L22 Symbol Min Max VA 1.65 2.63 +VHP 1.65 2.63 VP 1.60 5.25 VD 1.65 2.63 VL 1.65 3.47 T -40 +85 A Min Max -0.3 3.0 -0.3 5 ...
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... Refer to Table “Headphone Output Power Characteris- tics” on page 14 Refer to Table “Headphone Output Power Characteristics” on page 14 16 Ω kΩ 0.1 - ±100 (Note (Note CS43L22 = +25° kΩ for the line output 1.8 V Max Min Typ Max Unit - ...
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... Min Typ Max A-weighted - -96 unweighted - -93 -1 dBFS - -70 -20 dBFS - -73 -60 dBFS - -33 - 0.91•VA - 0.84•VA - 0/-0.3 A-weighted - -96 unweighted - -93 -1 dBFS - -70 -20 dBFS - -73 -60 dBFS - -33 - 0.91•VA - 0.84• 0/-0.3 CS43L22 will effectively 1.8 V Min Typ Max - - - - - - - 0.91• 0.84• 0/-0 - -91 - ...
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... THD+N < 10% THD+N < 1% THD+N < 10% THD+N < 1% THD dBFS = 0. dBFS = 0. dBFS = 0. -60 dBFS, A-Weighted -60 dBFS, Unweighted -60 dBFS, A-Weighted -60 dBFS, Unweighted 5.0V 0.5 A DS(ON 3.7V 0.5 A DS(ON) d CS43L22 = 4 Ω for mono parallel L Min Typ Max Units - 1. rms - 0. rms - 1. rms - 1. rms - 0. 0. 0.50 - ...
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... (see 2.5V Min Typ Max - (Note (Note (Note 4, 8) See Figures 18 AOUTx 51 Ω 0.022 μF AGND Figure 2. Headphone Output Test Load CS43L22 Min Typ Max Units = 0 760 - = - 1.5 - 0.8 5.0 Figure 2); “Required Initialization Settings” 1.8V Min Typ Max - ...
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... kHz Fs = 44.1 kHz kHz CS43L22 2); “Required Initialization Settings” 1.8V Unit Min Typ Max - 1.25 - 1.41 1.48 1. 1.73 - 2. ...
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... SCLK Frequency SCLK Duty Cycle SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge 11. After powering up the CS43L22, RESET should be held low after the power supplies and clocks are settled. 12. See “Example System Clock Frequencies” on page 61 ...
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... Repeated Start t high t hdst sud t sust low hdd Figure 4. Control Port Timing - I²C CS43L22 Min Max - 100 550 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop susp ...
Page 18
... Low-Level Input Voltage 15. See “I/O Pin Characteristics” on page 8 18 Confidential Draft 3/4/10 DAC (HP & Line Amps) DAC (HP & Line Amps) Full-Bridge PWM Outputs (Note 15) Symbol > 2.0 V for serial and control port power rails. CS43L22 Min Typ Max - 0.5• ...
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... CS43L22 Typical Current (mA Total VL=3.3V VP=3.7V Power (Note 19) (mW 0.00 0.00 0.00 0.00 0.00 0.00 ...
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... Basic Architecture The CS43L22 is a highly integrated, low power, 24-bit audio DAC comprised of a Digital Signal Processing Engine, headphone amplifiers, a digital PWM modulator and two full-bridge power back-ends. Other fea- tures include battery level monitoring and compensation and temperature monitoring. The DAC is de- signed using multi-bit delta-sigma techniques and operates at an oversampling ratio of 128Fs, where Fs is equal to the system sample rate ...
Page 21
... Chnl Vol. Settings PCMASWAP[1:0] PCMBSWAP[1:0] Σ Channel Swap MSTAMUTE MSTBMUTE BPVOL[4:0] DIGSFT 0dB/-50dB DIGZC 2.0dB steps PLYBCKB=A VOL Figure 5. DSP Engine Signal Flow CS43L22 LIMARATE[7:0] LIMRRATE[7:0] LMAX[2:0] CUSH[2:0] LIMSRDIS LIMZCDIS LIMIT Limiter PWM Modulator Peak Detect Bass/ VOL Treble/ Control ...
Page 22
... Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page 51 “PCMx Volume: PCMA (Address 1Ah) & PCMB (Address 1Bh)” on page 47 “Beep Off Time” on page 48 “Beep On Time” on page 48 “Beep Frequency” on page 47 “Beep Configuration” on page 49 “Beep Mix Disable” on page 49 “Beep Volume” on page 49 CS43L22 ... DS792F2 ...
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... L im ite DS792F2 Confidential Draft 3/4/10 Register Location “Limiter Control 2, Release Rate (Address 28h)” on page “Master Volume Control: MSTA (Address 20h) & MSTB (Address 21h)” on page Figure 7. Peak Detect & Limiter CS43L22 54, “Limiter Attack Rate (Address 29h)” on page ...
Page 24
... Four analog input channels can be chosen or summed by using the PASSxSEL bits as shown in to provide input to the CS43L22 when in analog passthrough mode. A pair of passthrough amplifiers can be used to mute and apply gain to the input signals. PASSASEL[4:1] ...
Page 25
... Mute” on page 44 PASSxVOL[7:0] ................... “Passthrough x Volume” on page 46 CHGFREQ .......................... “Charge Pump Frequency” on page 58 DS792F2 Confidential Draft 3/4/10 DAC VOL PASSTHRUA PASSTHRUB PASSAMUTE PASSBMUTE PASSAVOL[7:0] CHGFREQ[3:0] PASSBVOL[70] +12dB/-60dB 0.5dB steps Figure 9. Analog Outputs CS43L22 PDN_HPA[1:0] PDN_HPB[1:0] HPGAIN[2:0] A HP/Line Outputs B Charge Pump 25 ...
Page 26
... Power Control” on page 38 SPKxSHRT.......................... “Speaker Current Load Status (Read Only)” on page 57 26 Confidential Draft 3/4/10 BATTCMP VPREF[3:0] VPLVL[7:0] Battery Compensation PWM Gate Modulator Drive PDN_SPKA[1:0] PDN_SPKB[1:0] SPKASHRT SPKBSHRT Figure 10. PWM Output Stage CS43L22 + Speaker Outputs Short Circuit DS792F2 ...
Page 27
... Maintaining a Desired Output Level Using SPKxVOL, the speaker output level must first be attenuated by the decibel equivalent of the expect supply range (MAX relative to MIN). The CS43L22 then gradually reduces the attenuation as the VP supply drops from its maximum level, maintaining a nearly constant power output. ...
Page 28
... Register Location VPREF ................................ “VP Reference” on page 57 SPKxVOL ............................ “Speaker Volume Control” on page 52 28 Confidential Draft 3/4/10 4.6 4.3 4 3.7 3.4 3.1 2.8 VP Supply (V) Figure 11. Battery Compensation CS43L22 Battery Compensated PWM Output Level Uncompensated PWM Output Level 2.5 2.2 1.9 1.6 DS792F2 ...
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... Serial Port Clocking The CS43L22 serial audio interface port operates either as a slave or master, determined by the M/S bit. It accepts externally generated clocks in Slave Mode and will generate synchronous clocks derived from an input master clock (MCLK) in Master Mode. Refer to the tables below for the required setting in register 05h and 06h associated with a given MCLK and sample rate ...
Page 30
... SCLK SDIN 30 Confidential Draft 3/4/10 SPEED[1:0] 32kGROUP VIDEOCLK (AUTO=’0’ Table 1. Serial Port Clocking Figure 12. I²S Format LSB MSB Figure 13. Left-Justified Format UTA Audio W ord Length (AW L) Figure 14. Right-Justified Format\ CS43L22 RATIO[1:0] MCLKDIV2 AOUTB Right Channel MSB LSB AOUTB ...
Page 31
... Audio Word Length (AWL) 4.8 Initialization The CS43L22 enters a Power-Down state upon initial power-up. The interpolation and decimation filters, delta-sigma and PWM modulators and control port registers are reset. The internal voltage reference, and switched-capacitor low-pass filters are powered down. The device will remain in the Power-Down state until the RESET pin is brought high. The control port is ac- ...
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... All performance and power consumption measurements were taken with the following settings: 1. Write 0x99 to register 0x00. 2. Write 0x80 to register 0x47. 3. Write ‘1’b to bit 7 in register 0x32. 4. Write ‘0’b to bit 7 in register 0x32. 5. Write 0x00 to register 0x00. 32 Confidential Draft 3/4/10 CS43L22 3 to avoid premature disruption DS792F2 ...
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... SDA while the clock is high. A Stop condition is defined as a rising transition of SDA while the clock is high. All other transitions of SDA occur while the clock is low. The first byte sent to the CS43L22 after a Start condition consists of a 7-bit chip address field and a R/W bit (high for a read, low for a write). ...
Page 34
... The device has MAP auto-increment capability enabled by the INCR bit (the MSB) of the MAP. If INCR is set to 0, MAP will stay constant for successive I²C writes or reads. If INCR is set to 1, MAP will auto-in- crement after each byte is read or written, allowing block reads or writes of successive registers. 34 Confidential Draft 3/4/10 CS43L22 DS792F2 ...
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... Reserved Reserved Reserved Reserved PCMAVOL5 PCMAVOL4 PCMAVOL3 PCMBVOL5 PCMBVOL4 PCMBVOL3 PCMBVOL2 PCMBVOL1 FREQ1 FREQ0 OFFTIME0 BPVOL4 BEEPMIXDIS TREB_CF1 TREB_CF0 TREB1 TREB0 CS43L22 CHIPID0 REVID2 REVID1 PDN3 PDN2 PDN1 Reserved Reserved Reserved RATIO1 RATIO0 DACDIF1 DACDIF0 AWL1 Reserved Reserved ANLGZCB ANLGSFTA Reserved ...
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... DSPAOVFL PCMAOVFL PCMBOVFL Reserved Reserved VPREF3 VPLVL5 VPLVL4 VPLVL3 SPKASHRT SPKBSHRT SPKR/ Reserved Reserved Reserved Reserved Reserved Reserved CHGFREQ1 CHGFREQ0 Reserved CS43L22 MSTAVOL2 MSTAVOL1 MSTAVOL0 MSTBVOL2 MSTBVOL1 MSTBVOL0 HPAVOL2 HPAVOL1 HPAVOL0 HPBVOL2 HPBVOL1 HPBVOL0 SPKAVOL2 SPKAVOL1 SPKAVOL0 SPKBVOL2 SPKBVOL1 SPKBVOL0 Reserved ...
Page 37
... B1 7.2 Power Control 1 (Address 02h PDN7 PDN6 PDN5 7.2.1 Power Down Configures the power state of the CS43L22. PDN[7:0] Status 0000 0001 Powered Down - same as setting 1001 1111 1001 1110 Powered Up 1001 1111 Powered Down - same as setting 0000 0001 Note: 1. All states of PDN[7:0] not shown in the table are reserved. ...
Page 38
... Notes: 1. The SPEED[1:0] bits are ignored and speed is determined by the MCLK/LRCK ratio. 2. When AUTO is disabled and the CS43L22 operates in Master Mode, the MCLKDIV2 bit is ignored. 3. Certain sample and MCLK frequencies require setting the SPEED[1:0] bits, the 32k_GROUP bit (“32kHz Sample Rate Group” on page ...
Page 39
... MCLK/LRCK Ratio 512 256 128 128 “Master/Slave Mode” on page 39) and/or the VIDEOCLK bit (“Internal MCLK/LRCK Ratio” on page (“Auto-Detect” on page SCLK/LRCK Ratio in Master Mode CS43L22 SCLK/LRCK Ratio 40. (“27 MHz Video Clock” on 39). Low sample rates may also 38) is enabled. 39 ...
Page 40
... Interface Formats” on page 30 Note: Select the audio word length for Right Justified using the AWL[1:0] bits page 41). 40 Confidential Draft 3/4/ DSP DACDIF1 (“Audio Word Length” on page CS43L22 (“Auto-Detect” on page 38) is disabled DACDIF0 AWL1 AWL0 41). (“Audio Word Length” on DS792F2 0 ...
Page 41
... This bit is only valid for MCLK = 12.0000 MHz. 7.6.2 Speaker/Headphone Switch Invert Determines the control signal polarity of the SPK/HP_SW pin. INV_SWCH SPK/HP_SW pin 6 Control 0 Not inverted 1 Inverted DS792F2 Confidential Draft 3/4/10 Right Justified 24-bit data 20-bit data 18-bit data 16-bit data Reserved INV_SWCH Reserved CS43L22 1 0 Reserved Reserved 41 ...
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... Disabled 1 Enabled 42 Confidential Draft 3/4/ Reserved PASSASEL4 PASSASEL3 PASSASEL2 PASSASEL1 Reserved ANLGSFTB Affected Analog Volume Controls PASSxVOL[7:0] (“Passthrough x Volume” on page Affected Analog Volume Controls PASSxVOL[7:0] (“Passthrough x Volume” on page Reserved Reserved CS43L22 ANLGZCB ANLGSFTA ANLGZCA 46) 46 Reserved Reserved Reserved DS792F2 ...
Page 43
... Configures a digital mute on the master volume control for channel x. MSTxMUTE Master Mute 0 Not Inverted 1 Inverted Note: The muting function is affected by the DIGSFT (“Digital Zero Cross” on page DS792F2 Confidential Draft 3/4/ PLYBCKB=A INV_PCMB 14. (“Digital Soft Ramp” on page 45) bits. CS43L22 INV_PCMA MSTBMUTE MSTAMUTE and “Headphone Output Power 44) and DIGZC 43 ...
Page 44
... Playback Mute” on page HPxMUTE, SPKxMUTE PCMxMUTE, PCMxVOL[7:0] MSTxVOL[7:0] (“Master Volume Control” on page HPxVOL[7:0] (“Headphone Volume Control” on page SPKxVOL[7:0] (“Speaker Volume Control” on page CS43L22 DEEMPH DIGSFT DIGZC 43), (“Playback Control 2 (Address 0Fh)” on page (“PCM Channel x Volume” on page ...
Page 45
... Volume Control” on page HPxVOL[7:0] (“Headphone Volume Control” on page SPKxVOL[7:0] (“Speaker Volume Control” on page (“Limiter Soft Ramp Disable” on page SPKAMUTE SPKB=A CS43L22 43), (“Playback Control 2 (Address 0Fh)” on page (“PCM Channel x Volume” on page 47), 51), 51), 52), 53) is ignored when zero cross is enabled ...
Page 46
... This register is ignored when the PASSTHRUx bit 2. The step size may deviate from 0 settings below -40 dB. Code settings 0x95, 0xA1, 0xAD and 0xB9 are not guaranteed to be monotonic. 46 Confidential Draft 3/4/ PASSxVOL4 PASSxVOL3 (“Passthrough Analog” on page CS43L22 PASSxVOL2 PASSxVOL1 PASSxVOL0 44) is disabled. DS792F2 ...
Page 47
... Hz 1000 1043.48 Hz 1001 1200.00 Hz 1010 1333.33 Hz 1011 1411.76 Hz 1100 1600.00 Hz 1101 1714.29 Hz 1110 2000.00 Hz 1111 2181.82 Hz Application: “Beep Generator” on page 22 DS792F2 Confidential Draft 3/4/ PCMxVOL4 PCMxVOL3 FREQ0 ONTIME3 CS43L22 2 1 PCMxVOL2 PCMxVOL1 PCMxVOL0 2 1 ONTIME2 ONTIME1 ONTIME0 Pitch ...
Page 48
... Sets the off duration of the beep signal. OFFTIME[2:0] Off Time ( kHz) 000 ~1.23 s 001 ~2.58 s 010 ~3.90 s 011 ~5.20 s 100 ~6.60 s 101 ~8.05 s 110 ~9.35 s 111 ~10.80 s Application: “Beep Generator” on page 22 48 Confidential Draft 3/4/ BPVOL4 BPVOL3 CS43L22 BPVOL2 BPVOL1 BPVOL0 DS792F2 ...
Page 49
... Mix Disabled; The output alternates between the signal from the serial data input and the beep signal. The 1 beep signal does not mix with the digital signal from the serial data input. Application: “Beep Generator” on page 22 Note: This setting must not change when BEEP is enabled. DS792F2 Confidential Draft 3/4/ TREBCF1 TREBCF0 CS43L22 BASSCF1 BASSCF0 TCEN 49 ...
Page 50
... Sets the gain of the treble shelving filter. TREB[3:0] Gain Setting 0000 +12.0 dB ··· ··· 0111 +1.5 dB 1000 0 dB 1001 -1.5 dB ··· ··· 1111 -10.5 dB Step Size: 1 Confidential Draft 3/4/ TREB0 BASS3 CS43L22 BASS2 BASS1 BASS0 DS792F2 ...
Page 51
... Muted Step Size: 0.5 dB DS792F2 Confidential Draft 3/4/ MSTxVOL4 MSTxVOL3 HPxVOL4 HPxVOL3 CS43L22 MSTxVOL2 MSTxVOL1 MSTxVOL0 HPxVOL2 HPxVOL1 HPxVOL0 51 ...
Page 52
... PCM Channel Swap Configures a mix/swap of the PCM data to the headphone/line or speaker outputs. PCMxSWP[1:0] PCM to HP/LINEOUTA 00 Left 01 (Left + Right)/ Right 52 Confidential Draft 3/4/ SPKxVOL4 SPKxVOL3 PCMBSWP0 Reserved CS43L22 2 1 SPKxVOL2 SPKxVOL1 SPKxVOL0 2 1 Reserved Reserved Reserved PCM to HP/LINEOUTB Right (Left + Right)/2 Left DS792F2 0 0 ...
Page 53
... Note: This bit is ignored when the DIGZC DS792F2 Confidential Draft 3/4/ CUSH2 CUSH1 54). 54) until levels lie between the LMAX and CUSH thresholds. (“Digital Soft Ramp” on page (“Digital Zero Cross” on page CS43L22 CUSH0 LIMSRDIS LIMZCDIS 44) setting 45) is enabled. 53 ...
Page 54
... DIGSFT (“Digital Soft Ramp” on page 54 Confidential Draft 3/4/10 (“Digital Zero Cross” on page LIMRRATE4 LIMRRATE3 53) and returns the analog output level to the MSTxVOL[7:0] 51) setting. 44) and DIGZC CS43L22 45) setting LIMRRATE2 LIMRRATE1 LIMRRATE0 (“Digital Zero Cross” on page 45) setting. DS792F2 ...
Page 55
... Application: “DSP Engine” on page 21 DS792F2 Confidential Draft 3/4/ LIMARATE4 LIMARATE3 53). 44) and DIGZC (“Digital Zero Cross” on page (“Limiter Soft Ramp Disable” on page DSPBOVFL PCMAOVFL CS43L22 LIMARATE2 LIMARATE1 LIMARATE0 45) setting unless or “Limiter Zero Cross Disable” PCMBOVFL Reserved Reserved 55 ...
Page 56
... VPMONITOR setting. Conversely, when BATTCMP is disabled, the ADC may be en- abled by enabling VPMONITOR; this provides a convenient battery monitor without enabling battery compensation. 2. When enabled, VPMONITOR remains enabled regardless of the PDN bit setting. 56 Confidential Draft 3/4/ Reserved VPREF3 CS43L22 (“PCM Channel x Volume” on page 47) of the VPREF2 VPREF1 VPREF0 DS792F2 ...
Page 57
... Speaker Current Load Status (Read Only) Indicates whether or not any of the speaker outputs is shorted to ground. SPKxSHRT Speaker Output Load 0 No overload detected 1 Overload detected DS792F2 Confidential Draft 3/4/10 (for VA = 1.8 V) (for VPLVL4 VPLVL3 SPKBSHRT SPKR/HP CS43L22 VPLVL2 VPLVL1 VPLVL0 Reserved Reserved Reserved 57 ...
Page 58
... CHGFREQ3 CHGFREQ2 CHGFREQ1 7.30.1 Charge Pump Frequency Sets the charge pump frequency on FLYN and FLYP. CHGFREQ[3:0] N 0000 0 ... 0101 5 ... 1111 15 Formula: Frequency = (64xFs)/(N+2) Note: The headphone output THD+N performance may be affected. 58 Confidential Draft 3/4/ CHGFREQ0 Reserved CS43L22 Reserved Reserved Reserved DS792F2 ...
Page 59
... W 40m 50m 60m 70m 80m W CS43L22 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 23 mW into single 16 Ω and 46 mW into stereo 16 Ω with THD dB) ...
Page 60
... W 30m 35m 40m 45m 50m 55m 60m W CS43L22 G = 0.6047 G = 0.7099 G = 0.8399 G = 1.0000 G = 1.1430 Legend NOTE: Graph shows the out- put power per channel (i.e. Output Power = 22 mW into single 32 Ω and 44 mW into stereo 32 Ω with THD dB) ...
Page 61
... MCLK (MHz) 256x 384x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 MCLK (MHz) 128x 192x 8.1920 12.2880 11.2896 16.9344 12.2880 18.4320 CS43L22 2048x* 3072x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 1024x* 1536x* 16.3840 24.5760 22.5792 33.8688 24.5760 36.8640 512x* 768x* 16.3840 24 ...
Page 62
... QFN Thermal Pad The CS43L22 is available in a compact QFN package. The underside of the QFN package reveals a large metal pad that serves as a thermal relief to provide for maximum heat dissipation. This pad must mate with an equally dimensioned copper pad on the PCB and must be electrically connected to ground. A series of vias should be used to connect this copper pad to one or more larger ground planes on other PCB layers ...
Page 63
... FILTER PLOTS Figure 22. Passband Ripple Figure 24. DAC Transition Band DS792F2 Confidential Draft 3/4/10 Figure 23. Stopband Figure 25. Transition Band (Detail) CS43L22 63 ...
Page 64
... Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channel pairs. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. 64 Confidential Draft 3/4/10 CS43L22 DS792F2 ...
Page 65
... MIN -- 0.0394 -- -- 0.0020 0.00 0.0110 0.18 0.1634 4.05 0.1634 4.05 0.0197 0.30 JEDEC #: MO-220 Controlling Dimension is Millimeters. Symbol 2 Layer Board 4 Layer Board CS43L22 b e PIN #1 CORNER D2 MILLIMETERS NOM MAX -- 1.00 -- 0.05 0.23 0.28 6.00 BSC 4.10 4.15 6.00 BSC 4.10 4.15 ...
Page 66
... Control” on page 33. “Register Quick Reference” on page 35 11. “Register Quick Reference” on page www.cirrus.com. CS43L22 Temp Range Container Order # Rail CS43L22-CNZ Tape & Reel CS43L22-CNZR - - CDB43L22 and Figure 17. Control Port Timing, I²C and “Register Description” on page 37 35. to DS792F2 ...