AD5333BRUZ Analog Devices Inc, AD5333BRUZ Datasheet - Page 15

IC DAC 10BIT DUAL VOUT 24-TSSOP

AD5333BRUZ

Manufacturer Part Number
AD5333BRUZ
Description
IC DAC 10BIT DUAL VOUT 24-TSSOP
Manufacturer
Analog Devices Inc
Datasheet

Specifications of AD5333BRUZ

Data Interface
Parallel
Settling Time
7µs
Number Of Bits
10
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
2.25mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
24-TSSOP
Resolution (bits)
10bit
Sampling Rate
143kSPS
Input Channel Type
Parallel
Supply Voltage Range - Analogue
2.5V To 5.5V
Supply Current
300µA
Digital Ic Case
RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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High-Byte Enable Input (HBEN)
High-Byte Enable is a control input on the AD5343 only that
determines if data is written to the high-byte input register or
the low-byte input register.
The low data byte of the AD5343 consists of data bits 0 to 7 at
data inputs DB
bits 8 to 11 at data inputs DB
during a high byte write, but they may be used for data to
set up the reference input as buffered/unbuffered, and buffer
amplifier gain. See Figure 32.
POWER-ON RESET
The AD5332/AD5333/AD5342/AD5343 are provided with a
power-on reset function, so that they power up in a defined state.
The power-on state is:
• Normal operation
• Reference input unbuffered
• 0 – V
• Output voltage set to 0 V
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
REV. 0
CLR
1
1
0
1
1
1
X = don’t care.
CLR
1
1
0
1
1
1
1
1
X = don’t care.
REF
output range
Figure 30. Data Format for AD5343
LDAC
1
1
X
1
1
1
1
0
X = UNUSED BIT
0
DB7
X
to DB
LDAC
1
1
X
1
1
0
DB6
X
7
DB5
, while the high byte consists of data
X
HIGH BYTE
LOW BYTE
DB4
CS
1
X
X
0
0
0
0
X
0
X
to DB
DB11
DB3
DB10
CS
1
X
X
0
0
X
3
DB2
. DB
DB9
DB1
4
Table I. AD5332/AD5333/AD5342 Truth Table
to DB
WR
X
1
X
0➝1
0➝1
0➝1
0➝1
X
DB0
DB8
7
Table II. AD5343 Truth Table
are ignored
WR
X
1
X
0➝1
0➝1
X
A0
X
X
X
0
0
1
1
X
–15–
POWER-DOWN MODE
The AD5332/AD5333/AD5342/AD5343 have low power con-
sumption, dissipating typically 0.69 mW with a 3 V supply and
1.5 mW with a 5 V supply. Power consumption can be further
reduced when the DACs are not in use by putting them into
power-down mode, which is selected by taking pin PD low.
When the PD pin is high, the DACs work normally with a typical
power consumption of 300 µA at 5 V (230 µA at 3 V). In power-
down mode, however, the supply current falls to 200 nA at 5 V
(80 nA at 3 V) when both DACs are powered down. Not only
does the supply current drop, but the output stage is also internally
switched from the output of the amplifier, making it open-circuit.
This has the advantage that the outputs are three-state while
the part is in power-down mode, and provides a defined input
condition for whatever is connected to the outputs of the DAC
amplifiers. The output stage is illustrated in Figure 31.
The bias generator, the output amplifier, the resistor string, and
all other associated linear circuitry are all shut down when the
power-down mode is activated. However, the contents of the
registers are unaffected when in power-down. The time to exit
power-down is typically 2.5 µs for V
V
when the output voltage deviates from its power-down voltage.
See Figure 22.
DD
= 3 V. This is the time from a rising edge on the PD pin to
A0
X
X
X
0
1
X
AD5332/AD5333/AD5342/AD5343
Figure 31. Output Stage During Power-Down
HBEN
X
X
X
0
1
0
1
X
STRING DAC
RESISTOR
Function
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Input Register
Load DAC B Input Register
Update DAC Registers
Function
No Data Transfer
No Data Transfer
Clear All Registers
Load DAC A Low Byte Input Register
Load DAC A High Byte Input Register
Load DAC B Low Byte Input Register
Load DAC B High Byte Input Register
Update DAC Registers
AMPLIFIER
DD
POWER-DOWN
CIRCUITRY
= 5 V and 5 µs when
VOUT

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