CS4385-DQZ Cirrus Logic Inc, CS4385-DQZ Datasheet

IC DAC 8CH 114DB 192KHZ 48LQFP

CS4385-DQZ

Manufacturer Part Number
CS4385-DQZ
Description
IC DAC 8CH 114DB 192KHZ 48LQFP
Manufacturer
Cirrus Logic Inc
Datasheet

Specifications of CS4385-DQZ

Data Interface
Serial
Number Of Bits
24
Number Of Converters
8
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
520mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
48-LQFP
Resolution (bits)
24bit
Sampling Rate
192kSPS
Input Channel Type
Serial
Supply Voltage Range - Analog
4.75V To 5.25V
Supply Current
84mA
Digital Ic Case Style
QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
598-1154 - BOARD EVAL FOR CS4385 DAC
Settling Time
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
598-1649

Available stocks

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Quantity
Price
Part Number:
CS4385-DQZ
Manufacturer:
Cirrus Logic Inc
Quantity:
135
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CS4385-DQZ
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Maxim
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Part Number:
CS4385-DQZ
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Part Number:
CS4385-DQZR
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Quantity:
10 000
Features
Advanced Multi-bit Delta Sigma Architecture
24-bit Conversion
Automatic Detection of Sample Rates up to
192 kHz
114 dB Dynamic Range
-100 dB THD+N
Direct Stream Digital Mode
Compatible with Industry-Standard Time
Division Multiplexed (TDM) Serial Interface
Selectable Digital Filters
Volume Control with 1/2-dB Step Size and Soft
Ramp
Low Clock-Jitter Sensitivity
+5 V Analog Supply, +2.5 V Digital Supply
Separate 1.8 to 5 V Logic Supplies for the
Control and Serial Ports
http://www.cirrus.com
Non-Decimating Volume Control
On-Chip 50 kHz Filter
Matched PCM and DSD Analog Output
Levels
I
2
C/SPI Software Mode
Serial Audio Port
Supply = 1.8 V to 5 V
Hardware Mode or
Control Data
Audio Input
Audio Input
PCM Serial
TDM Serial
DSD Audio
Control Port Supply = 1.8 V to 5 V
114 dB, 192 kHz 8-Channel D/A Converter
Reset
Input
8
Register/Hardware
DSD Processor
Controls
Configuration
Volume
-Volume control
-50 kHz filter
Digital Supply = 2.5 V
Copyright © Cirrus Logic, Inc. 2008
Digital
Filters
(All Rights Reserved)
Multi-bit ΔΣ
Modulators
Description
The CS4385 is a complete 8-channel digital-to-analog
system. This D/A system includes digital de-emphasis,
half-dB step size volume control, ATAPI channel mix-
ing, selectable fast and slow digital interpolation filters
followed by an oversampled, multi-bit delta sigma mod-
ulator which includes mismatch-shaping technology
that eliminates distortion due to capacitor mismatch.
Following this stage is a multi-element switched capac-
itor stage and low-pass filter with differential analog
outputs.
The CS4385 also has a proprietary DSD processor
which allows for volume control and 50 kHz on-chip fil-
tering without an intermediate decimation stage. It also
offers an optional path for direct DSD conversion by di-
rectly using the multi-element switched capacitor array.
The CS4385 is available in a 48-pin LQFP package in
both Commercial (-40°C to +85°C) and Automotive
(-40°C to +105°C) grades. The CDB4385 Customer
Demonstration board is also available for device evalu-
ation and implementation suggestions. Please see
“Ordering Information” on page 54
The CS4385 accepts PCM data at sample rates from
4 kHz to 216 kHz, DSD audio data, and delivers excel-
lent sound quality. These features are ideal for multi-
channel audio systems, including SACD players, A/V
receivers, digital TV’s, mixing consoles, effects proces-
sors, sound cards, and automotive audio systems.
Analog Supply = 5 V
Internal Voltage
Reference
Analog Filters
Switch-Cap
DAC and
External Mute
Control
8
8
2
Mute Signals
Eight Channels
of Differential
Outputs
CS4385
for complete details.
DS671F2
FEB '08

Related parts for CS4385-DQZ

CS4385-DQZ Summary of contents

Page 1

... It also offers an optional path for direct DSD conversion by di- rectly using the multi-element switched capacitor array. The CS4385 is available in a 48-pin LQFP package in both Commercial (-40°C to +85°C) and Automotive (-40°C to +105°C) grades. The CDB4385 Customer Demonstration board is also available for device evalu- ation and implementation suggestions ...

Page 2

... SPI Mode ............................................................................................................................. 34 4.14.3.1 SPI Write .................................................................................................................. 34 4.15 Memory Address Pointer (MAP) .................................................................................................. 34 4.15.1 INCR (Auto Map Increment Enable) .................................................................................... 34 4.15.2 MAP4-0 (Memory Address Pointer) .................................................................................... 34 5. REGISTER QUICK REFERENCE ....................................................................................................... 35 6. REGISTER DESCRIPTION .................................................................................................................. 37 6.1 Chip Revision (address 01h) ......................................................................................................... 37 6.1.1 Part Number ID (PART) [Read Only] .................................................................................... 37 2 ...................................................................................................................... 6 CS4385 DS671F2 ...

Page 3

... Volume Control (address 0Bh, 0Ch, 0Eh, 0Fh, 11h, 12h, 14h, 15h) ............................................ 46 6.11.1 Digital Volume Control (xx_VOL7:0) ................................................................................... 46 6.12 PCM Clock Mode (address 16h) .................................................................................................. 47 6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV) ................................................................ 47 7. FILTER PLOTS ..................................................................................................................................... 48 8. PARAMETER DEFINITIONS ................................................................................................................ 52 9. PACKAGE DIMENSIONS ................................................................................................................... 53 10. ORDERING INFORMATION .............................................................................................................. 54 11. REFERENCES .................................................................................................................................... 54 12. REVISION HISTORY ......................................................................................................................... 54 DS671F2 CS4385 3 ...

Page 4

... Figure 44.Quad-Speed (fast) Stopband Rejection .................................................................................... 50 Figure 45.Quad-Speed (fast) Transition Band .......................................................................................... 50 Figure 46.Quad-Speed (fast) Transition Band (detail) .............................................................................. 51 Figure 47.Quad-Speed (fast) Passband Ripple ........................................................................................ 51 Figure 48.Quad-Speed (slow) Stopband Rejection ................................................................................... 51 Figure 49.Quad-Speed (slow) Transition Band ......................................................................................... 51 Figure 50.Quad-Speed (slow) Transition Band (detail) ............................................................................. 51 Figure 51.Quad-Speed (slow) Passband Ripple ....................................................................................... 51 4 CS4385 DS671F2 ...

Page 5

... Table 4. PCM Digital Interface Format, Hardware Mode Options ............................................................. 22 Table 5. Mode Selection, Hardware Mode Options .................................................................................. 22 Table 6. Direct Stream Digital (DSD), Hardware Mode Options ............................................................... 22 Table 7. Digital Interface Formats - PCM Mode ........................................................................................ 39 Table 8. Digital Interface Formats - DSD Mode ........................................................................................ 39 Table 9. ATAPI Decode Table .................................................................................................................. 45 Table 10. Example Digital Volume Settings .............................................................................................. 46 DS671F2 CS4385 5 ...

Page 6

... The use of external mute circuits are not mandatory but may be desired for designs requiring the absolute minimum in extraneous clicks and pops GND CS4385 Pin Description CS4385 AOUTA2- AOUTA2+ AOUTB2+ AOUTB2- VA GND AOUTA3- AOUTA3+ AOUTB3+ AOUTB3- AOUTA4- AOUTA4+ Tables 1-3 illus- DS671F2 ...

Page 7

... DSD Serial Clock (Input) - Serial clock for the Direct Stream Digital audio interface. DSDA1 3 DSDB1 2 DSDA2 1 DSDB2 48 Direct Stream Digital Input (Input) - Input for Direct Stream Digital serial audio data. DSDA3 47 DSDB3 46 DSDA4 45 DSDB4 44 DS671F2 Pin Description ® Mode as shown in the Typical Connection Diagram. ™ Mode. CS4385 7 ...

Page 8

... Analog power VA Digital internal power VD VLS Control port interface power VLC Any Pin Except Supplies I in Serial data port interface V IND-S Control port interface V IND stg CS4385 Min Typ Max 4.75 5.0 5.25 2.37 2.5 2.63 1.71 5.0 5.25 1.71 5.0 5.25 - ...

Page 9

... THD+N 16-bit 0 dB -20 dB -60 dB A-weighted (1 kHz) PCM, DSD processor 1.28• Direct DSD Mode 0.90•V Z OUT I OUTmax QMAX and includes attenuation due CS4385 = 25°C; Full-scale 997 Hz A Min Typ Max 108 114 - 105 111 - - -100 - -51 -45 - -94 ...

Page 10

... THD+N 16-bit 0 dB -20 dB -60 dB A-weighted (1 kHz) PCM, DSD processor 1.28• Direct DSD Mode 0.90•V Z OUT I OUTmax QMAX CS4385 ; Tested under max ac-load (Note 1) ; Measure- Typ Max Units 114 - 111 - - -100 - -51 -42 - -94 - ...

Page 11

... Valid with the recommended capacitor values on FILT+ and VQ as shown in DS671F2 Symbol normal operation, VA VD= 2 Interface current, VLC VLS power-down state (all supplies 2.5 V normal operation (Note 6) power-down θ multi-layer JA θ dual-layer JA θ kHz) PSRR (60 Hz) CS4385 Min Typ Max Units - μ μ μA - 200 - - 470 520 ...

Page 12

... kHz - Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .583 (Note 10 6.15/Fs to -0.01 dB corner corner kHz -0.01 .635 (Note 10 7.1/Fs Section 7. “Filter Plots” on page CS4385 Unit Typ Max - .454 Fs - .499 Fs - +0. ±0. ±0. ±0. .430 Fs - .499 ...

Page 13

... Fs = 44.1 kHz - kHz - to -0.01 dB corner corner kHz -0.01 .792 (Note 10 5.4/Fs to -0.01 dB corner corner kHz -0.01 .868 (Note 10 6.6/Fs Min corner kHz -0. -0.1 dB corner corner 0 -0.1 CS4385 (Note 8) Unit Typ Max - 0.417 Fs - 0.499 Fs - +0. ±0. ±0. ±0. .296 Fs - .499 Fs - +0.01 ...

Page 14

... Any pin except supplies. Transient currents ±100 mA on the input pins will not cause SCR latch- up. 14 Symbol (Note 13 Serial I/O V 0.70•V IH Control I/O V 0.70•V IH Serial I Control I Control I 0.70• max CS4385 Min Typ Max Units μ ± 0.30• 0.30• 0.20• 0.25• ...

Page 15

... Single-Speed Mode Double-Speed Mode Quad-Speed Mode Single-Speed Mode Double-Speed Mode Quad-Speed Mode (Note 16) (Note 17 lcks sckh sckl MSB Figure 1. Serial Audio Interface Timing Figure 2. TDM Serial Audio Interface Timing CS4385 Symbol Min Max 1 - 1.024 55 108 s F 100 216 108 Fs 170 216 ...

Page 16

... DSD_SCLK (64Fs) DSDxx Figure 4. Direct Stream Digital - Serial Audio Input Timing for Phase Modulation Mode Symbol t sclkl t sclkh (64x Oversampled) (128x Oversampled) t sdlrs t sdh t dpm t t sdlrs sdh t t dpm dpm CS4385 Min Typ Max 160 - - 160 - - 1.024 - 3.2 2.048 - 6 - ...

Page 17

... Repeated t high t t sud t sust hdd Figure 5. Control Port Timing - I²C Format CS4385 Min Max - 100 500 - 4.7 - 4.0 - 4.7 - 4 250 - - 1 - 300 4.7 - 300 1000 , of SCL. fc Stop Start ...

Page 18

... L Symbol f sclk t srs (Note 19) t spi t csh t css t scl t sch t dsu (Note 20 (Note 21 (Note 21 css t scl t sch dsu t dh Figure 6. Control Port Timing - SPI Format CS4385 Min Max Unit - 6 MHz 500 - ns 500 - ns 1.0 - µ 100 ns - 100 all other times. ...

Page 19

... MUTEC1 44 DSDB4 MUTEC234 42 DSD_SCLK 19 RST 15 SCL/CCLK 16 SDA/CDIN 17 ADO/CS Note* FILT+ 18 VLC 0.1 µF TST* GND GND CS4385 + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning 30 and Muting 28 Analog Conditioning ...

Page 20

... AOUTB4+ 42 DSD_SCLK AOUTB4- Optional 47 KΩ MUTEC234 RST FILT+ 18 VLC 0.1 µF GND GND 5 31 CS4385 + 0.1 µF 1 µF 39 Analog Conditioning 40 and Muting 38 Analog Conditioning 37 and Muting Mute 41 Drive 35 Analog Conditioning 36 and Muting 34 Analog Conditioning 33 and Muting 29 Analog Conditioning 30 and Muting ...

Page 21

... SDINx, and the Serial Clock (SCLK) clocks audio data into the input data buffer. For more information on serial audio interfaces, see Cirrus Application Note AN282, “The 2-Channel Serial Audio Interface: A Tutorial.” The CS4385 can be configured in Hardware Mode by the M0, M1, M2, M3 and M4 pins and in Software Mode through I²C or SPI. ...

Page 22

... DSD data with a 2x MCLK to DSD data rate 0 128x oversampled DSD data with a 3x MCLK to DSD data rate 1 128x oversampled DSD data with a 4x MCLK to DSD data rate 0 128x oversampled DSD data with a 6x MCLK to DSD data rate 1 CS4385 FORMAT FIGURE DESCRIPTION ...

Page 23

... LRCK Left Channel SCLK SDINx Figure 13. Format 4 - Right-Justified 20-bit Data DS671F2 Left Channel + LSB MSB Left Channel + LSB MSB Figure 10. Format 1 - I² 24-bit Data clocks CS4385 Figures Right Channel + LSB Right Channel - LSB Right Channel Right Channel Right Channel 9-19. 23 ...

Page 24

... Figure 15. Format 8 - One-Line Mode 1 128 clks Left Channel LSB MSB LSB MSB DAC_A2 DAC_A3 DAC_B1 24 clks 24 clks 24 clks DAC_B4 24 clks Figure 16. Format 9 - One-Line Mode 2 CS4385 Right Channel clks Right Channel LSB MSB LSB MSB LSB DAC_B2 DAC_B3 20 clks 20 clks 128 clks ...

Page 25

... Figure 17. Format 10 - One-Line Mode 3 LSB MSB LSB MSB LSB MSB DAC_A3 DAC_A4 DAC_B1 24 clks 24 clks 24 clks Figure 18. Format 11 - One Line Mode 4 CS4385 128 clks Right Channel LSB MSB LSB MSB LSB MSB LSB DAC_B2 DAC_B3 DAC_B4 20 clks 20 clks 20 clks ...

Page 26

... The auto-speed mode detect feature allows for the automatic selection of speed mode based off of the in- coming sample rate. This allows the CS4385 to accept a wide range of sample rates with no external inter- vention necessary. The auto-speed mode detect feature is available in both hardware and Software Mode. ...

Page 27

... De-Emphasis The CS4385 includes on-chip digital de-emphasis filters. The de-emphasis feature is included to accommo- date older audio recordings that utilize pre-emphasis equalization as a means of noise reduction. shows the de-emphasis curve. The frequency response of the de-emphasis curve will scale proportionally with changes in sample rate the input sample rate does not match the coefficient which has been se- lected ...

Page 28

... CS4385, but may lower the sensitivity to board-level routing of the DSD data signals. The CS4385 can detect errors in the DSD data which does not comply with the SACD specification. The STATIC_DSD and INVALID_DSD bits (Reg. 04h) allow the CS4385 to alter the incoming invalid DSD data. ...

Page 29

... The Typical Connection Diagram shows the rec- ommended power arrangements, with VA, VD, VLC, and VLS connected to clean supplies. If the ground planes are split between digital ground and analog ground, the GND pins of the CS4385 should be connect the analog ground plane. ...

Page 30

... The external mute circuitry needs to be self-biased into an active state in order to be muted during reset. Upon release of reset, the CS4385 will detect the status of the MUTEC pins (high or low) and will then select that state as the polarity to drive when the mutes become active. The ex- ternal-bias voltage level that the MUTEC pins see at the time of release of reset must meet the “ ...

Page 31

... Bring RST high. The device will remain in a low power state with FILT+ low and will initiate the Hardware power-up sequence after approximately 512 LRCK cycles in Single-Speed Mode (1024 LRCK cycles in Double-Speed Mode, and 2048 LRCK cycles in Quad-Speed Mode). DS671F2 Figure 25. Recommended Mute Circuitry CS4385 Section 4.1. In this state, the 31 ...

Page 32

... If the device ever detects a high-to-low transition on the AD0/CS pin after power-up, SPI Mode will be selected. 32 Section 4.1. In this state, the registers are reset to the default 48). The operation of the control port may be completely asynchronous with Figure 26 for the clock to data relationship). There pin. The AD0 pin CS4385 DS671F2 ...

Page 33

... DS671F2 4.14.1) is set to 1, repeat the previous step until all the desired registers Section 4.14. I²C read is the first operation performed on the N ote 1 ADDR DATA R/W ACK ACK AD 0 1-8 Figure 26. Control Port Timing, I²C Mode CS4385 DATA ACK 1-8 Stop 33 ...

Page 34

... Default = ‘00000’ 34 4.14.1) is set to 1, repeat the previous step until all the desired registers CHIP MAP ADDRESS 0011000 R/W MSB byte ory Address Pointer Figure 27. Control Port Timing, SPI Mode MAP4 MAP3 CS4385 DATA LSB byte MAP2 MAP1 MAP0 DS671F2 ...

Page 35

... P2_DEM1 P2_DEM0 P2ATAPI4 P2ATAPI3 A2_VOL6 A2_VOL5 A2_VOL4 B2_VOL6 B2_VOL5 B2_VOL4 P3_DEM1 P3_DEM0 P3ATAPI4 P3ATAPI3 A3_VOL6 A3_VOL5 A3_VOL4 B3_VOL6 B3_VOL5 B3_VOL4 P4_DEM1 P4_DEM0 P4ATAPI4 P4ATAPI3 CS4385 PART0 REV REV Reserved Reserved FM1 INVALID_D DSD_PM_ DSD_PM_ Reserved Reserved Reserved INV_B2 INV_A2 INV_B1 0 ...

Page 36

... Addr Function 7 14h Vol. Control A4 A4_VOL7 default 0 15h Vol. Control B4 B4_VOL7 default 0 16h PCM clock mode Reserved default A4_VOL6 A4_VOL5 A4_VOL4 A4_VOL3 B4_VOL6 B4_VOL5 B4_VOL4 B4_VOL3 Reserved MCLKDIV Reserved Reserved CS4385 A4_VOL2 A4_VOL1 A4_VOL0 B4_VOL2 B4_VOL1 B4_VOL0 Reserved Reserved Reserved DS671F2 ...

Page 37

... Chip Revision (address 01h PART4 PART3 PART2 0 0 6.1.1 Part Number ID (PART) [Read Only] 00001- CS4385 Revision ID (REV) [Read Only] 000 - Revision A0 001 - Revision B0 Function: This read-only register can be used to identify the model and revision number of the device. 6.2 Mode Control 1 (address 02h) 7 ...

Page 38

... The required relationship between the Left/Right clock, serial clock and serial data is defined by the Digital Interface Format and the options are detailed in Note: While in PCM Mode, the DIF bits should only be changed when the power-down (PDN) bit is set to ensure proper switching from one mode to another DIF0 Reserved Figures 9 through 19. CS4385 Digital In Reserved FM1 FM0 DS671F2 ...

Page 39

... DSD data with a 2x MCLK to DSD data rate 1 128x oversampled DSD data with a 3x MCLK to DSD data rate 0 128x oversampled DSD data with a 4x MCLK to DSD data rate 1 128x oversampled DSD data with a 6x MCLK to DSD data rate Table 8. Digital Interface Formats - DSD Mode CS4385 FORMAT ...

Page 40

... DSD Phase Modulation Mode Enable (DSD_PM_EN) Function: When set to 1, DSD phase modulation input mode is enabled, and the DSD_PM_MODE bit should be set accordingly. When set to 0 (default), this function is disabled (DSD normal mode). 40 28) CS4385 Section 1), the dynamic range DS671F2 ...

Page 41

... DAC pair mute control signals is output on the MUTEC1 pin, MUTEC234 will remain static. For more in- formation on the use of the mute control function see the MUTEC1 and MUTEC234 pins in DS671F2 Reserved Reserved INV_A3 INV_B2 P1_A=B P2_A CS4385 Reserved Reserved FILT_SEL INV_A2 INV_B1 INV_A1 P3_A=B P4_A=B SNGLVOL 0 0 ...

Page 42

... The zero cross function is independently monitored and implemented for each channel. Soft Ramp Soft Ramp allows level changes, both muting and attenuation implemented by incrementally ramp- ing, in 1/8 dB steps, from the current level to the new level at a rate per 8 left/right clock periods RMP_DN PAMUTE CS4385 DAMUTE MUTE_P1 MUTE_P0 DS671F2 ...

Page 43

... A single sample of non-static data will release the mute. De- tection and muting is done independently for each channel. The quiescent voltage on the output will be retained and the Mute Control pin will go active during the mute period. When set to 0, this function is disabled. DS671F2 CS4385 43 ...

Page 44

... The Digital-to-Analog converter output will mute when enabled. The quiescent voltage on the output will be retained. The muting function is affected, similarly to attenuation changes, by the Soft and Zero Cross bits. The MUTE pins will go active during the mute period according to the MUTEC bit. 44 for description MUTE_A3 MUTE_B2 CS4385 MUTE_A2 MUTE_B1 MUTE_A1 DS671F2 ...

Page 45

... De-emphasis is only available in Single-Speed Mode. 6.10.2 ATAPI Channel Mixing and Muting (ATAPI) Default = 01001 - AOUTAx=aL, AOUTBx=bR (Stereo) Function: The CS4385 implements the channel-mixing functions of the ATAPI CD-ROM specification. The ATAPI functions are applied per A-B pair. Refer to ATAPI4 ATAPI3 ATAPI2 ...

Page 46

... Table 9. ATAPI Decode Table xx_VOL4 xx_VOL3 Table 10 are approximate. The actual attenuation is determined Decimal Value 00000000 0 00000001 1 00000110 6 11111111 255 Table 10. Example Digital Volume Settings CS4385 AOUTAx AOUTBx MUTE [(bL+aR)/2] aR MUTE [(aL+bR)/2] aL MUTE [(aL+bR)/2] [(aL+bR)/2] MUTE [(aL+bR)/2] bR [(bL+aR)/2] ...

Page 47

... Master Clock DIVIDE by 2 ENABLE (MCLKDIV) Function: When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. When set to 0 (default), MCLK is unchanged. DS671F2 Reserved Reserved CS4385 Reserved Reserved Reserved ...

Page 48

... Figure 31. Single-Speed (fast) Passband Ripple 0 −20 −40 −60 −80 −100 −120 0.8 0.9 1 0.4 0.42 Figure 33. Single-Speed (slow) Transition Band CS4385 0.44 0.46 0.48 0.5 0.52 0.54 0.56 0.58 Frequency(normalized to Fs) 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0 ...

Page 49

... Figure 37. Double-Speed (fast) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.05 Figure 39. Double-Speed (fast) Passband Ripple CS4385 0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 Frequency(normalized to Fs) 0.44 0.46 0.48 0.5 0.52 0.54 0.56 ...

Page 50

... Figure 43. Double-Speed (slow) Passband Ripple 100 120 0.7 0.8 0.9 1 0.2 Figure 45. Quad-Speed (fast) Transition Band CS4385 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0.05 0.1 0.15 0.2 0.25 0.3 Frequency(normalized to Fs) 0.3 0.4 0.5 0.6 0.7 Frequency(normalized to Fs) 0 ...

Page 51

... Figure 49. Quad-Speed (slow) Transition Band 0.02 0.015 0.01 0.005 0 0.005 0.01 0.015 0.02 0.52 0.53 0.54 0.55 0 0.02 Figure 51. Quad-Speed (slow) Passband Ripple CS4385 0.05 0.1 0.15 0.2 0.25 Frequency(normalized to Fs) 0.3 0.3 0.4 0.4 0.5 0.5 0.6 0.6 0.7 0.7 ...

Page 52

... Units in decibels. Interchannel Gain Mismatch The gain difference between left and right channels. Units in decibels. Gain Drift The change in gain value with temperature. Units in ppm/°C. 52 CS4385 DS671F2 ...

Page 53

... Nominal pin pitch is 0.50 mm *Controlling dimension is mm. *JEDEC Designation: MS022 CS4385 A A1 MILLIMETERS MIN NOM MAX --- 1.40 1.60 0.05 0.10 0.15 0.17 0.22 0.27 8.70 9.0 BSC 9 ...

Page 54

... LQFP Automotive -40°C to +105° Changes “Recommended Operating Conditions” on page page 55 “Mode Select” on page 22 “Power and Thermal Characteristics” on page 11 CS4385 Temp Range Container Order # Tray CS4385-CQZ Tape & Reel CS4385-CQZR Tray CS4385-DQZ Tape & Reel CS4385-DQZR - - CDB4385 DS671F2 8. ...

Page 55

... Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. I² registered trademark of Philips Semiconductor. SPI is a trademark of Motorola, Inc. DS671F2 www.cirrus.com CS4385 55 ...

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