AD5339ARM Analog Devices Inc, AD5339ARM Datasheet - Page 17

IC DAC 12BIT DUAL 2-WIRE 8-MSOP

AD5339ARM

Manufacturer Part Number
AD5339ARM
Description
IC DAC 12BIT DUAL 2-WIRE 8-MSOP
Manufacturer
Analog Devices Inc
Datasheets

Specifications of AD5339ARM

Data Interface
Serial
Rohs Status
RoHS non-compliant
Settling Time
8µs
Number Of Bits
12
Number Of Converters
2
Voltage Supply Source
Single Supply
Power Dissipation (max)
1.9mW
Operating Temperature
-40°C ~ 105°C
Mounting Type
Surface Mount
Package / Case
8-MSOP, Micro8™, 8-uMAX, 8-uSOP,
Resolution (bits)
12bit
Sampling Rate
14.8kSPS
Input Channel Type
Serial
Supply Voltage Range - Analogue
2.5V To 5.5V
Supply Current
300µA
Digital Ic Case
RoHS Compliant
Lead Free Status / RoHS Status

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Default Readback Condition
All pointer byte bits power up to 0. Therefore, if the user
initiates a readback without writing to the pointer byte first, no
single DAC channel has been specified. In this case, the default
readback bits are all 0s, except for the CLR bit, which is 1.
Multiple DAC Write Sequence
Because there are individual bits in the pointer byte for each
DAC, it is possible to write the same data and control bits to two
DACs simultaneously by setting the relevant bits to 1.
SDA
SDA
SCL
SCL
CONDITION
MASTER
START
BY
0
MOST SIGNIFICANT DATA BYTE
MSB
0
MSB
PD1
MSB
PD1
MSB
PD1
0
PD0
PD0
PD0
ADDRESS BYTE
MOST SIGNIFICANT DATA BYTE
1
CLR
CLR
CLR LDAC
10-BIT AD5338
12-BIT AD5339
8-BIT AD5337
LDAC
LDAC
1
D11
0
D7
D9
Figure 32. Data Formats for Write and Read Back
D10
A0
D6
D8
D7
D9
D5
R/W
LSB
Figure 33. Write Sequence
Rev. C | Page 17 of 28
AD533x
AD533x
LSB
LSB
LSB
D6
D8
D4
ACK
ACK
BY
BY
MSB
X
LEAST SIGNIFICANT DATA BYTE
MSB
MSB
MSB
MSB
D7
D3
D5
Multiple DAC Read Back Sequence
If the user attempts to read back data from more than one DAC
at a time, the part reads back the default, power-on reset
conditions, that is, all 0s except for CLR , which is 1.
WRITE OPERATION
When writing to the AD5337/AD5338/AD5339 DACs, the user
must begin with an address byte (R/ W = 0), after which the
DAC acknowledges that it is prepared to receive data by pulling
SDA low. This address byte is followed by the pointer byte,
which is also acknowledged by the DAC. Two bytes of data are
then written to the DAC, as shown in Figure 33. A stop
condition follows.
X
D6
D2
D4
LEAST SIGNIFICANT DATA BYTE
D5
D1
D3
POINTER BYTE
10-BIT AD5338
12-BIT AD5339
8-BIT AD5337
D0
D2
D4
D3
D1
X
AD5337/AD5338/AD5339
D2
D0
X
D1
X
X
LSB
LSB
LSB
D0
X
X
LSB
LSB
AD533x
AD533x
ACK
ACK
BY
BY
CONDITION
MASTER
STOP
BY

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