AD9760ARU Analog Devices Inc, AD9760ARU Datasheet

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AD9760ARU

Manufacturer Part Number
AD9760ARU
Description
IC DAC 10BIT 125MSPS 28-TSSOP
Manufacturer
Analog Devices Inc
Series
TxDAC®r
Datasheet

Specifications of AD9760ARU

Settling Time
35ns
Rohs Status
RoHS non-compliant
Number Of Bits
10
Number Of Converters
1
Voltage Supply Source
Analog and Digital
Power Dissipation (max)
175mW
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
28-TSSOP
Number Of Channels
1
Resolution
10b
Interface Type
Parallel
Single Supply Voltage (typ)
5V
Dual Supply Voltage (typ)
Not RequiredV
Power Supply Requirement
Analog and Digital
Output Type
Current
Single Supply Voltage (min)
2.7V
Single Supply Voltage (max)
5.5V
Dual Supply Voltage (min)
Not RequiredV
Dual Supply Voltage (max)
Not RequiredV
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
28
For Use With
AD9760-EBZ - BOARD EVAL FOR AD9760
Data Interface
-
Lead Free Status / RoHS Status
Not Compliant

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Price
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AD9760ARU
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AD
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Part Number:
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a
PRODUCT DESCRIPTION
The AD9760 and AD9760-50 are the 10-bit resolution members
of the TxDAC series of high performance, low power CMOS
digital-to-analog converters (DACs). The AD9760-50 is a lower
performance option that is guaranteed and specified for 50 MSPS
operation. The TxDAC family that consists of pin compatible 8-,
10-, 12- and 14-bit DACs is specifically optimized for the trans-
mit signal path of communication systems. All of the devices
share the same interface options, small outline package and
pinout, thus providing an upward or downward component
selection path based on performance, resolution and cost. Both
the AD9760 and AD9760-50 offer exceptional ac and dc
performance while supporting update rates up to 125 MSPS
and 60 MSPS respectively.
The AD9760’s flexible single-supply operating range of 2.7 V to
5.5 V and low power dissipation are well suited for portable and
low power applications. Its power dissipation can be further
reduced to a mere 45 mW without a significant degradation in
performance by lowering the full-scale current output. Also, a
power-down mode reduces the standby power dissipation to
approximately 25 mW.
The AD9760 is manufactured on an advanced CMOS process. A
segmented current source architecture is combined with a propri-
etary switching technique to reduce spurious components and
enhance dynamic performance. Edge-triggered input latches and a
1.2 V temperature compensated bandgap reference have been inte-
grated to provide a complete monolithic DAC solution. Flexible
supply options support +3 V and +5 V CMOS logic families.
TxDAC is a registered trademark of Analog Devices, Inc.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FEATURES
Member of Pin-Compatible TxDAC Product Family
125 MSPS Update Rate
10-Bit Resolution
Excellent Spurious Free Dynamic Range Performance
SFDR to Nyquist @ 40 MHz Output: 52 dBc
Differential Current Outputs: 2 mA to 20 mA
Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V
Power-Down Mode: 25 mW @ 5 V
On-Chip 1.20 V Reference
Single +5 V or +3 V Supply Operation
Packages: 28-Lead SOIC and TSSOP
Edge-Triggered Latches
APPLICATIONS
Communication Transmit Channel:
Direct Digital Synthesis (DDS)
Instrumentation
Basestations
Set Top Boxes
Digital Radio Link
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/326-8703
The AD9760 is a current-output DAC with a nominal full-scale
output current of 20 mA and > 100 kΩ output impedance.
Differential current outputs are provided to support single-
ended or differential applications. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The current outputs may be
tied directly to an output resistor to provide two complemen-
tary, single-ended voltage outputs or fed directly into a trans-
former. The output voltage compliance range is 1.25 V.
The on-chip reference and control amplifier are configured for
maximum accuracy and flexibility. The AD9760 can be driven
by the on-chip reference or by a variety of external reference
voltages. The internal control amplifier that provides a wide
(>10:1) adjustment span allows the AD9760 full-scale current
to be adjusted over a 2 mA to 20 mA range while maintaining
excellent dynamic performance. Thus, the AD9760 may oper-
ate at reduced power levels or be adjusted over a 20 dB range to
provide additional gain ranging capabilities.
The AD9760 is available in a 28-lead SOIC and TSSOP packages.
It is specified for operation over the industrial temperature range.
PRODUCT HIGHLIGHTS
1. The AD9760 is a member of the TxDAC product family that
2. Manufactured on a CMOS process, the AD9760 uses a pro-
3. On-chip, edge-triggered input CMOS latches interface readily
4. A flexible single-supply operating range of 2.7 V to 5.5 V and
5. The current output(s) of the AD9760 can be easily config-
CLOCK
provides an upward or downward component selection path
based on resolution (8 to 14 bits), performance and cost.
prietary switching technique that enhances dynamic perfor-
mance beyond what was previously attainable by higher
power/cost bipolar or BiCMOS devices.
to +3 V and +5 V CMOS logic families. The AD9760 can
support update rates up to 125 MSPS.
a wide full-scale current adjustment span of 2 mA to 20 mA
allow the AD9760 to operate at reduced power levels.
ured for various single-ended or differential circuit topologies.
R
SET
0.1 F
+5V
FUNCTIONAL BLOCK DIAGRAM
REFIO
FS ADJ
DVDD
DCOM
CLOCK
SLEEP
+1.20V REF
TxDAC
World Wide Web Site: http://www.analog.com
REFLO
DIGITAL DATA INPUTS (DB9–DB0)
SEGMENTED
SWITCHES
10-Bit, 125 MSPS
50pF
®
LATCHES
D/A Converter
COMP1
0.1 F
CURRENT
© Analog Devices, Inc., 2000
SOURCE
ARRAY
SWITCHES
LSB
AD9760
+5V
AVDD
AD9760
COMP2
ACOM
I
I
OUTA
OUTB
0.1 F

Related parts for AD9760ARU

AD9760ARU Summary of contents

Page 1

FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 10-Bit Resolution Excellent Spurious Free Dynamic Range Performance SFDR to Nyquist @ 40 MHz Output: 52 dBc Differential Current Outputs Power Dissipation: 175 ...

Page 2

AD9760/AD9760-50–SPECIFICATIONS DC SPECIFICATIONS ( MIN Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) MONOTONICITY ANALOG OUTPUT Offset Error Gain Error (Without Internal Reference) Gain Error (With Internal Reference) 2 Full-Scale Output Current Output Compliance ...

Page 3

DYNAMIC SPECIFICATIONS Model Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f CLOCK Output Settling Time (t ) (to 0.1%) ST Output Propagation Delay ( Glitch Impulse 1 Output Rise Time (10% to 90%) 1 Output Fall Time (10% ...

Page 4

... Model Max Units AD9760AR +6.5 V +6.5 V AD9760ARU +0.3 V +6.5 V AD9760AR50 DVDD + 0.3 V DVDD + 0.3 V AD9760ARU50 –40°C to +85°C AVDD + 0.3 V AVDD + 0.3 V AD9760-EB AVDD + 0.3 V +0.3 V °C +150 THERMAL CHARACTERISTICS °C +150 Thermal Resistance 28-Lead 300 mil (7.5 mm) SOIC °C +300 θ ...

Page 5

Pin No. Name Description 1 DB9 Most Significant Data Bit (MSB). 2–9 DB8–DB1 Data Bits 1–8. 10 DB0 Least Significant Data Bit (LSB). 11–14 Internal Connection. 15 SLEEP Power-Down Control Input. Active High. Contains active pull-down circuit, ...

Page 6

AD9760 DEFINITIONS OF SPECIFICATIONS Linearity Error (Also Called Integral Nonlinearity or INL) Linearity error is defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. ...

Page 7

Typical AC Characterization Curves @ +5 V Supplies (AVDD = +5 V, DVDD = + mA, 50 OUTFS 90 5MSPS 80 25MSPS 70 50MSPS 100MSPS 60 125MSPS 50 0 100 FREQUENCY – MHz Figure ...

Page 8

AD9760 –70 –75 2ND HARMONIC –80 3RD HARMONIC –85 4TH –90 HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 12. THD vs CLOCK MHz OUT 0.5 0.4 0.3 0.2 ...

Page 9

Typical AC Characterization Curves @ +3 V Supplies (AVDD = +3 V, DVDD = + mA, 50 OUTFS 90 5MSPS 80 25MSPS 70 100MSPS 50MSPS 60 125MSPS 50 0 100 FREQUENCY – MHz Figure ...

Page 10

AD9760 –70 –75 2ND HARMONIC 3RD –80 HARMONIC –85 –90 4TH HARMONIC – 100 120 140 FREQUENCY – MSPS Figure 30. THD vs. f CLOCK MHz OUT 0.5 0.4 0.3 0.2 0.1 ...

Page 11

FUNCTIONAL DESCRIPTION Figure 39 shows a simplified block diagram of the AD9760. The AD9760 consists of a large PMOS current source array that is capable of providing total current. The array is divided into 31 ...

Page 12

AD9760 The differential voltage appearing across I DIFF I is: OUTB ) × – I DIFF OUTA OUTB LOAD Substituting the values OUTA OUTB expressed as: = {(2 DAC CODE ...

Page 13

AVDD 1.2V AD1580 The optimum distortion performance for any reconstructed waveform is obtained with a 0.1 µF external capacitor installed. is fixed for an application, a 0.1 µF ceramic chip Thus REF capacitor is recommended. Also, since the ...

Page 14

AD9760 The enhancement in distortion performance becomes more significant as the frequency content of the reconstructed wave- form increases. This is due to the first order cancellation of various dynamic common-mode distortion mechanisms, digi- tal feedthrough and noise. Performing a ...

Page 15

Note, the clock input could also be driven via a sine wave that is centered around the digital threshold (i.e., DVDD/2), and meets the min/max logic threshold. This will typically result in a slight degradation in the phase noise, that ...

Page 16

AD9760 APPLYING THE AD9760 OUTPUT CONFIGURATIONS The following sections illustrate some typical output configura- tions for the AD9760. Unless otherwise noted assumed that I is set to a nominal 20 mA. For applications requir- OUTFS ing the optimum ...

Page 17

I and R can be selected as long as the positive compli- OUTFS LOAD ance range is adhered to. One additional consideration in this mode is the integral nonlinearity (INL) as discussed in the Ana- log Output section of this ...

Page 18

AD9760 APPLICATIONS Using the AD9760 for QAM Modulation QAM is one of the most widely used digital modulation schemes in digital communication systems. This modulation technique can be found in both FDM spreadspectrum (i.e., CDMA) based systems. A QAM signal ...

Page 19

REV. B Figure 59. Evaluation Board Schematic –19– AD9760 ...

Page 20

AD9760 Figure 60. Silkscreen Layer—Top Figure 61. Component Side PCB Layout (Layer 1) –20– REV. B ...

Page 21

REV. B Figure 62. Ground Plane PCB Layout (Layer 2) Figure 63. Power Plane PCB Layout (Layer 3) –21– AD9760 ...

Page 22

AD9760 Figure 64. Solder Side PCB Layout (Layer 4) Figure 65. Silkscreen Layer—Bottom –22– REV. B ...

Page 23

Thin Shrink Small Outline Package (TSSOP) 0.006 (0.15) 0.002 (0.05) SEATING PLANE REV. B OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 28-Lead, 300 Mil SOIC (R-28) 0.7125 (18.10) 0.6969 (17.70 0.2992 (7.60) ...

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