AD9744ARU Analog Devices Inc, AD9744ARU Datasheet
AD9744ARU
Specifications of AD9744ARU
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AD9744ARU Summary of contents
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FEATURES High performance member of pin-compatible TxDAC product family Excellent spurious-free dynamic range performance SFDR to Nyquist 83 dBc @ 5 MHz output 80 dBc @ 10 MHz output 73 dBc @ 20 MHz output SNR @ 5 MHz output, ...
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AD9744 TABLE OF CONTENTS Specifications..................................................................................... 3 DC Specifications ......................................................................... 3 Dynamic Specifications ............................................................... 4 Digital Specifications ................................................................... 5 Absolute Maximum Ratings............................................................ 6 Thermal Characteristics .............................................................. 6 ESD Caution.................................................................................. 6 Pin Configurations and Function Descriptions ........................... 7 Terminology ...................................................................................... 8 Typical ...
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SPECIFICATIONS DC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX Table 1. Parameter RESOLUTION 1 DC ACCURACY Integral Linearity Error (INL) Differential Nonlinearity (DNL) ANALOG OUTPUT Offset Error ...
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AD9744 DYNAMIC SPECIFICATIONS AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3 MIN MAX terminated, unless otherwise noted. Table 2. Parameter DYNAMIC PERFORMANCE Maximum Output Update Rate (f ) CLOCK 1 Output ...
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Parameter Multitone Power Ratio (8 Tones at 400 kHz Spacing MSPS 15.0 MHz to 18.2 MHz CLOCK OUT 0 dBFS Output −6 dBFS Output −12 dBFS Output −18 dBFS Output 1 Measured single-ended into 50 ...
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AD9744 ABSOLUTE MAXIMUM RATINGS Table 4. Parameter AVDD DVDD CLKVDD ACOM ACOM DCOM AVDD AVDD DVDD CLOCK, SLEEP Digital Inputs, MODE IOUTA, IOUTB REFIO, REFLO, FS ADJ CLK+, CLK−, CMODE Junction Temperature Storage Temperature Lead Temperature (10 sec) Stresses above ...
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PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS (MSB) DB13 1 28 DB12 2 27 DB11 3 26 DB10 4 25 DB9 5 24 AD9744 DB8 6 23 TOP VIEW DB7 7 22 (Not to Scale) DB6 8 21 DB5 9 20 DB4 ...
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AD9744 TERMINOLOGY Linearity Error (Also Called Integral Nonlinearity or INL defined as the maximum deviation of the actual analog output from the ideal output, determined by a straight line drawn from zero to full scale. Differential Nonlinearity (or ...
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TYPICAL PERFORMANCE CHARACTERISTICS 95 210MSPS (LFCSP) 90 125MSPS 85 165MSPS (LFCSP) 80 65MSPS 75 210MSPS 70 165MSPS 65 125MSPS (LFCSP (MHz) OUT Figure 6. SFDR vs dBFS OUT 95 90 ...
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AD9744 65MSPS 210MSPS (LFCSP 210MSPS 65 165MSPS –25 –20 –15 –10 A (dBFS) OUT Figure 12. Single-Tone SFDR vs. A OUT 95 90 65MSPS 85 125MSPS (LFCSP ...
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TEMPERATURE (°C) Figure 18. SFDR vs. Temperature @ 165 MSPS, 0 dBFS 0 f CLOCK – 15.0MHz OUT ...
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AD9744 V REFIO I REF 0.1µF R SET 2kΩ 3.3V CLOCK 3.3V REFLO AVDD 150pF +1.2V REF AD9744 REFIO PMOS FS ADJ CURRENT SOURCE ARRAY DVDD LSB SEGMENTED SWITCHES DCOM FOR DB13–DB5 SWITCHES CLOCK LATCHES SLEEP DIGITAL DATA INPUTS (DB13–DB0) ...
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FUNCTIONAL DESCRIPTION Figure 24 shows a simplified block diagram of the AD9744. The AD9744 consists of a DAC, digital control logic, and full-scale output current control. The DAC contains a PMOS current source array capable of providing ...
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AD9744 The control amplifier allows a wide (10:1) adjustment span of I over range by setting I OUTFS 62.5 µA and 625 µA. The wide adjustment span of I vides several benefits. The first ...
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The output impedance of IOUTA and IOUTB is determined by the equivalent parallel combination of the PMOS switches associated with the current sources and is typically 100 kΩ in parallel with 5 pF also slightly dependent on the ...
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AD9744 AD9744 CLK+ CLOCK RECEIVER CLK– 50Ω 50Ω 1.3V NOM TT Figure 29. Clock Termination in PECL Mode DAC TIMING Input Clock and Data Timing Relationship Dynamic performance in a DAC is dependent on the relation- ship between ...
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DIFF PECL 100 150 f (MSPS) CLOCK Figure 33. I vs. f and Clock Mode CLKVDD CLOCK APPLYING THE AD9744 Output Configurations The following sections ...
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AD9744 capabilities should all be considered when optimizing this circuit. The differential circuit shown in Figure 36 provides the neces- sary level shifting required in a single-supply system. In this case, AVDD, which is the positive analog supply for both ...
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Note that the ratio in Figure 39 is calculated as amps out/volts in. Noise on the analog power supply has the effect of modulat- ing the internal switches, and therefore the output current. The voltage noise on AVDD, therefore, will ...
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AD9744 EVALUATION BOARD GENERAL DESCRIPTION The TxDAC family evaluation boards allow for easy setup and testing of any TxDAC product in the SOIC and LFCSP pack- ages. Careful attention to layout and circuit design, combined with a prototyping area, allows ...
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AVDD + C14 C16 C17 10µF 0.1µF 0.1µF 16V DVDD + C15 C18 C19 10µF 0.1µF 0.1µF 16V CKEXT CLOCK JP4 1 28 DB13 CLOCK DB13 2 27 DB12 DVDD DB12 DVDD 3 26 DB11 DCOM DB11 4 25 DB10 ...
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AD9744 Figure 43. SOIC Evaluation Board—Primary Side Figure 44. SOIC Evaluation Board—Secondary Side Rev Page ...
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Figure 45. SOIC Evaluation Board—Ground Plane Figure 46. SOIC Evaluation Board—Power Plane Rev Page AD9744 ...
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AD9744 Figure 47. SOIC Evaluation Board Assembly—Primary Side Figure 48. SOIC Evaluation Board Assembly—Secondary Side Rev Page ...
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RED L1 TP12 BEAD TB1 1 BLK C2 C3 10µF 0.1µF TP2 6.3V TB1 2 RED L2 TP13 BEAD TB3 1 BLK C7 C4 0.1µF 10µF TP4 6.3V TB3 2 RED L3 TP5 BEAD TB4 1 BLK C9 C5 0.1µF ...
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AD9744 32 1 DB7 DB8 DB7 2 31 DB6 DB9 DB6 30 3 DVDD DB10 DVDD 4 29 DB5 DB11 DB5 5 28 DB4 DB12 DB4 27 6 DB3 DB13 DB3 7 26 DB2 DCOM1 DB2 25 8 DB1 SLEEP ...
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Figure 52. LFCSP Evaluation Board Layout—Primary Side Figure 53. LFCSP Evaluation Board Layout—Secondary Side Rev Page AD9744 ...
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AD9744 Figure 54. LFCSP Evaluation Board Layout—Ground Plane Figure 55. LFCSP Evaluation Board Layout—Power Plane Rev Page ...
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Figure 56. LFCSP Evaluation Board Layout Assembly—Primary Side Figure 57. LFCSP Evaluation Board Layout Assembly—Secondary Side Rev Page AD9744 ...
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AD9744 OUTLINE DIMENSIONS PIN 1 0.15 0.05 COPLANARITY 0.30 (0.0118) 0.10 (0.0039) COPLANARITY 0.10 9.80 9.70 9. 4.50 4.40 4. 0.65 BSC 1.20 MAX 0.30 0.20 SEATING 0.19 0.09 PLANE 0.10 COMPLIANT TO ...
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... AD9744ARZRL 1 −40°C to +85°C AD9744ARU −40°C to +85°C AD9744ARURL7 −40°C to +85°C 1 AD9744ARUZ −40°C to +85°C 1 AD9744ARUZRL7 −40°C to +85°C AD9744ACP −40°C to +85°C AD9744ACPRL7 −40°C to +85°C 1 AD9744ACPZ −40°C to +85°C 1 AD9744ACPZRL7 − ...
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AD9744 NOTES ©2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C02913–0–4/05(B) Rev Page ...