M36L0T7050B2ZAQF Micron Technology Inc, M36L0T7050B2ZAQF Datasheet
M36L0T7050B2ZAQF
Specifications of M36L0T7050B2ZAQF
Related parts for M36L0T7050B2ZAQF
M36L0T7050B2ZAQF Summary of contents
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Mbit (Multiple Bank, Multi-Level, Burst) Flash memory and 32 Mbit (2Mb x16) PSRAM, Multi-Chip Package Feature summary ■ Multi-Chip Package – 1 die of 128 Mbit (8Mb x16, Multiple Bank, Multi-level, Burst) Flash Memory – 1 die of 32 ...
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Contents Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36L0T7050T2, M36L0T7050B2 7 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables List of tables Table 1. Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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M36L0T7050T2, M36L0T7050B2 List of figures Figure 1. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Summary description 1 Summary description The M36L0T7050T2 and M36L0T7050B2 combine two memory devices in a Multi-Chip Package: ● a 128-Mbit, Multiple Bank, Multi-Level, Burst, Flash memory, the M58LT128HT or M58LT128HB ● a 32-Mbit PseudoSRAM, the M69KW048BD. The purpose of this ...
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M36L0T7050T2, M36L0T7050B2 Table 1. Signal names (1) A0-A22 DQ0-DQ15 V DDF V DDQ V PPF CCP NC DU Flash memory signals WAIT F ...
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Summary description Figure 2. TFBGA Connections (Top view through package 8/22 2 ...
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M36L0T7050T2, M36L0T7050B2 2 Signal descriptions See Figure 1: Logic diagram connected to this device. 2.1 Address Inputs (A0-A22) Addresses A0-A20 are common inputs for the Flash memory and the PSRAM components. The other lines (A21-A22) are inputs for the Flash ...
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Signal descriptions 2.6 Flash Write Protect (WP Write Protect is an input that gives an additional hardware protection for each block. When Write Protect is Low, V Down blocks cannot be changed. When Write Protect is at High, V and ...
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M36L0T7050T2, M36L0T7050B2 2.12 PSRAM Chip Enable Input (E2 The Chip Enable, E2 This is the lowest power mode. 2.13 PSRAM Write Enable (W The Write Enable, W 2.14 PSRAM Output Enable (G The Output Enable, G cycles to be achieved ...
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Signal descriptions 2.20 V Program Supply Voltage PPF V is both a Flash control input and a Flash power supply pin. The two functions are PPF selected by the voltage range applied to the pin kept in ...
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M36L0T7050T2, M36L0T7050B2 3 Functional description The PSRAM and Flash memory components have separate power supplies but share the same grounds. They are distinguished by three Chip Enable inputs: E memory and E1 P Recommended operating conditions do not allow more ...
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Functional description Table 2. Operating modes G W Operation Flash Read Flash Write Flash Address Latch Flash Output V V ...
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M36L0T7050T2, M36L0T7050B2 4 Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other ...
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DC and AC parameters 5 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests ...
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M36L0T7050T2, M36L0T7050B2 Figure 5. AC measurement load circuit Table 5. Device Capacitance Symbol C Input Capacitance IN C Output Capacitance OUT 1. Sampled only, not 100% tested. Please refer to the M58LT128HTB and M69KW048BD datasheets for further DC and AC ...
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Package mechanical 6 Package mechanical In order to meet environmental requirements, Numonyx offers these devices in ECOPACK® packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box ...
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M36L0T7050T2, M36L0T7050B2 Table 6. Stacked TFBGA88 8x10mm - 8x10 active ball array, 0.8mm pitch, Package Data Symbol ddd E 10.000 FE1 SD SE millimeters Typ Min Max 1.200 0.200 ...
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Part numbering 7 Part numbering Table 7. Ordering information scheme Example: Device Type M36 = Multi-Chip Package (Flash + RAM) Flash 1 Architecture L = Multilevel, Multiple Bank, Burst mode Flash 2 Architecture Die Operating Voltage T ...
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M36L0T7050T2, M36L0T7050B2 8 Revision history Table 8. Document revision history Date 04-May-2006 13-Nov-2007 Revision 01 Initial release. 02 Applied Numonyx branding. Revision history Changes 21/22 ...
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INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH NUMONYX™ PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN NUMONYX'S TERMS AND CONDITIONS OF SALE ...