GS8161Z36BGD-250 GSI TECHNOLOGY, GS8161Z36BGD-250 Datasheet

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GS8161Z36BGD-250

Manufacturer Part Number
GS8161Z36BGD-250
Description
Manufacturer
GSI TECHNOLOGY
Datasheet

Specifications of GS8161Z36BGD-250

Density
18Mb
Access Time (max)
5.5ns
Sync/async
Synchronous
Architecture
SDR
Clock Freq (max)
181MHz
Operating Supply Voltage (typ)
2.5/3.3V
Address Bus
19b
Package Type
FBGA
Operating Temp Range
0C to 70C
Number Of Ports
4
Supply Current
235mA
Operating Supply Voltage (min)
2.3/3V
Operating Supply Voltage (max)
2.7/3.6V
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
165
Word Size
36b
Number Of Words
512K
Lead Free Status / Rohs Status
Compliant
100-Pin TQFP & 165-Bump BGA
Commercial Temp
Industrial Temp
Features
• User-configurable Pipeline and Flow Through mode
• NBT (No Bus Turn Around) functionality allows zero wait
• Fully pin-compatible with both pipelined and flow through
• IEEE 1149.1 JTAG-compatible Boundary Scan
• 2.5 V or 3.3 V +10%/–10% core power supply
• LBO pin for Linear or Interleave Burst mode
• Pin-compatible with 2M, 4M, and 8M devices
• Byte write operation (9-bit Bytes)
• 3 chip enable signals for easy depth expansion
• ZZ pin for automatic power-down
• JEDEC-standard 100-lead TQFP and 165-bump FP-BGA
• RoHS-compliant 100-lead TQFP and 165-bump BGA
Functional Description
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is an 18Mbit Synchronous Static SRAM. GSI's NBT SRAMs,
like ZBT, NtRAM, NoBL or other pipelined read/double late
write or flow through read/single late write SRAMs, allow
utilization of all available bus bandwidth by eliminating the
need to insert deselect cycles when the device is switched from
read to write cycles.
Rev: 1.05a 10/2009
Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.
read-write-read bus utilization
NtRAM™, NoBL™ and ZBT™ SRAMs
packages
packages available
Flow Through
Pipeline
3-1-1-1
2-1-1-1
18Mb Pipelined and Flow Through
Curr
Curr
Synchronous NBT SRAM
Curr
Curr
tCycle
tCycle
Parameter Synopsis
t
(x32/x36)
(x32/x36)
t
KQ
KQ
(x18)
(x18)
1/38
GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
Because it is a synchronous device, address, data inputs, and
read/ write control inputs are captured on the rising edge of the
input clock. Burst order control (LBO) must be tied to a power
rail for proper operation. Asynchronous inputs include the
Sleep mode enable, ZZ and Output Enable. Output Enable can
be used to override the synchronous control of the output
drivers and turn the RAM's output drivers off at any time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-
chip write pulse generation required by asynchronous SRAMs
and simplifies input signal timing.
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
may be configured by the user to operate in Pipeline or Flow
Through mode. Operating as a pipelined synchronous device,
in addition to the rising-edge-triggered registers that capture
input signals, the device incorporates a rising-edge-triggered
output register. For read cycles, pipelined SRAM output data is
temporarily stored by the edge triggered output register during
the access cycle and then released to the output drivers at the
next rising edge of clock.
The GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)
is implemented with GSI's high performance CMOS
technology and is available in JEDEC-standard 100-pin TQFP
and 165-bump FP-BGA packages.
-250
295
345
225
255
2.5
4.0
5.5
5.5
-200
245
285
200
220
3.0
5.0
6.5
6.5
-150
200
225
185
205
3.8
6.7
7.5
7.5
Unit
mA
mA
mA
mA
ns
ns
ns
ns
© 2004, GSI Technology
250 MHz–150 MHz
2.5 V or 3.3 V V
2.5 V or 3.3 V I/O
DD

Related parts for GS8161Z36BGD-250

GS8161Z36BGD-250 Summary of contents

Page 1

... Curr (x18) 345 285 Curr (x32/x36) t 5.5 6.5 KQ 5.5 6.5 tCycle 225 200 Curr (x18) 255 220 Curr (x32/x36) 1/38 250 MHz–150 MHz 3.3 V I/O -150 Unit 3.8 ns 6.7 ns 200 mA 225 mA 7.5 ns 7.5 ns 185 mA 205 mA © 2004, GSI Technology DD ...

Page 2

... DDQ DDQ DDQ DQP DDQ Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) GS8161Z18BT Pinout (Package Top View 2/ DDQ DQP DDQ DDQ DDQ © 2004, GSI Technology ...

Page 3

... V DDQ DQP Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) GS8161Z36BT Pinout (Package T) 512K x 36 Top View 3/38 DQP DDQ DDQ DDQ DDQ DQP 51 A © 2004, GSI Technology ...

Page 4

... Byte D Data Input and Output pins Power down control; active high Pipeline/Flow Through Mode Control; active low Linear Burst Order; active low. Must Connect High (165 BGA only) Scan Test Mode Select 4/38 ; active low A9 ; active low B9 ; active low C9 ; active low D9 © 2004, GSI Technology ...

Page 5

... GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Description Scan Test Data In Scan Test Data Out Scan Test Clock Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply Ground Output driver power supply 5/38 © 2004, GSI Technology ...

Page 6

... GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/ CKE ADV TDI A1 TDO A A TMS A0 TCK A 6/ DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2004, GSI Technology ...

Page 7

... GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/ CKE ADV TDI A1 TDO A A TMS A0 TCK A 7/ DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ DDQ © 2004, GSI Technology ...

Page 8

... CKE ADV TDI A1 TDO A A TMS A0 TCK A 8/ DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2004, GSI Technology ...

Page 9

... Linear Burst Order mode; active low Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Must Connect High Core power supply I/O and Core Ground Output driver power supply 9/38 I/Os; active low D © 2004, GSI Technology ...

Page 10

... GS8161Z18/32/36B NBT SRAM Functional Block Diagram Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Amps Sense Drivers Write 10/38 © 2004, GSI Technology ...

Page 11

... Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/ & determine which bytes will be written. All or none may be activated 11/ and E ). Deassertion of any one of the Enable 2 3 © 2004, GSI Technology ...

Page 12

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) External L Next L External L Next L External L None L Next L Next L None L None L None L None L None Current L 12/ High High High High-Z 1,2,3, High High High High High © 2004, GSI Technology Notes 1,10 2 1,2, 1,3, ...

Page 13

... and D represent input command codes as indicated in the Synchronous Truth Table. n+1 n+2 ƒ ƒ Next State Pipelined and Flow Through Read/Write Control State Diagram 13/38 New Write Burst Write B D n+3 ƒ ƒ © 2004, GSI Technology ...

Page 14

... and D represent input command codes as indicated in the Truth Tables. Next State (n+2) n n+1 n+2 ƒ ƒ Intermediate Current State State Pipeline Mode Data I/O State Diagram 14/38 Intermediate R B Data Out W (Q Valid) D n+3 ƒ ƒ Next State © 2004, GSI Technology ...

Page 15

... Pipeline and Flow through Read Write Control State Diagram 15/ Data Out W (Q Valid) D Notes: 1. The Hold command (CKE Low) is not shown because it prevents any state change and D represent input command codes as indicated in the Truth Tables. n+2 n+3 ƒ ƒ © 2004, GSI Technology ...

Page 16

... H L SCD Activate DQPx I/Os (x18/x3672 mode Deactivate DQPx I/Os (x16/x3272 mode) 16/38 Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) © 2004, GSI Technology ...

Page 17

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Interleaved Burst Sequence 10 11 1st address 11 00 2nd address 00 01 3rd address 01 10 4th address Note: The burst counter wraps to initial state on the 5th clock. 17/38 A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 18

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Sleep Mode Timing Diagram tKH tKH tKL tKL tZZS tZZH 18/38 2. The duration of SB tZZR on pipelined parts and V on flow DDQ SS © 2004, GSI Technology ...

Page 19

... V maximum, with a pulse width not to exceed 50% tKC. DDn 19/38 Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 20

... Min. Typ – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 20/38 Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes   © 2004, GSI Technology ...

Page 21

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50 V DDQ/2 * Distributed Test Jig Capacitance 21/38 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

Page 22

... Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 22/38 Min –  V – V –1 uA 100 uA IH  V –100 uA IL V – – 2.375 V 1 3.135 V 2.4 V — © 2004, GSI Technology Max — — 0.4 V ...

Page 23

... GSI Technology –40 Unit to 85°C 215 mA 20 200 mA 15 195 mA 15 185 ...

Page 24

... GSI Technology ...

Page 25

... GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Pipeline Mode Timing (NBT) Write B+1 Read C Cont Read D tKL tKL tKH tKH tKC tKC tLZ tS tKQ D(A) D(B) D(B+1) Q(C) tOHZ 25/38 Write E Read F Write G Deselect tHZ tKQX Q(D) D(E) Q(F) tOLZ tOE © 2004, GSI Technology D(G) ...

Page 26

... Cont Read D tKL tKL tKH tKH tKC tKC C D tKQ tLZ D(B) D(B+1) Q(C) tOHZ 26/38 Write E Read F Write tKQX tKQ tHZ tLZ Q(D) D(E) Q(F) tOLZ tOE . The JTAG output DD . TDO should be left unconnected. SS © 2004, GSI Technology tKQX D(G) ...

Page 27

... Capture-DR state and then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. SAMPLE-Z, SAMPLE/PRELOAD and EXTEST instructions can be used to activate the Boundary Scan Register. Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Description 27/38 © 2004, GSI Technology ...

Page 28

... Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller Not Used Configuration 28/38 · · · TDO GSI Technology I/O JEDEC Vendor ID Code © 2004, GSI Technology ...

Page 29

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 29/38 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2004, GSI Technology ...

Page 30

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) 30/38 © 2004, GSI Technology ...

Page 31

... Instruction codes expressed in binary, MSB on left, LSB on right. 2. Default instruction automatically loaded at power-up and in test-logic-reset state. Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) Description 31/38 Notes © 2004, GSI Technology ...

Page 32

... DD3 0.8 V –0.3 0 +0.3 V DD2 DD2 0 –0.3 DD2 –300 1 uA 100 uA –1 – 1.7 V — 0.4 V — – 100 mV — V DDQ 100 mV V — JTAG Port AC Test Load DQ 50 30pF V /2 DDQ * Distributed Test Jig Capacitance © 2004, GSI Technology ...

Page 33

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) tTKC tTKC tTKH tTKH tTH tTS tTH tTS tTKQ tTH tTS Min Max Unit — — — — — — ns 33/38 tTKL tTKL © 2004, GSI Technology ...

Page 34

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D)  0.10 0.15 1.40 1.45 0.30 0.40 — 0.20 e 22.0 22.1 20.0 20.1 16.0 16.1 b 14.0 14.1 0.65 — 0.60 0.75 1.00 — 0.10 7 — 34/ © 2004, GSI Technology ...

Page 35

... A1 CORNER TOP VIEW SEATING PLANE C Rev: 1.05a 10/2009 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS8161Z18B(T/D)/GS8161Z32B(D)/GS8161Z36B(T/D) BOTTOM VIEW Ø0. Ø0. Ø0.40~0.60 (165x 1.0 10.0 13±0.05 B 0.20(4x) 35/38 A1 CORNER 1.0 © 2004, GSI Technology ...

Page 36

... GS8161Z36BD-250 512K x 36 GS8161Z36BD-200 512K x 36 GS8161Z36BD-150 512K x 36 GS8161Z36BGD-250 512K x 36 GS8161Z36BGD-200 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. 1. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 37

... GS8161Z36BGT-150I 512K x 36 GS8161Z36BD-250I 512K x 36 GS8161Z36BD-200I 512K x 36 GS8161Z36BD-150I 512K x 36 GS8161Z36BGD-250I 512K x 36 GS8161Z36BGD-200I 512K x 36 GS8161Z36BGD-150I Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. 1. The speed column indicates the cycle frequency (MHz) of the device in Pipeline mode and the latency (ns) in Flow Through mode. Each device is Pipeline/Flow Through mode-selectable by the user ...

Page 38

... Added Status column to Ordering Information table • Rev1.03a: updated coplanarity for 165 BGA mechanical, removed Status column from Ordering Information table. • Added MCH to Pin Description table Content • Updated to MP Status Content • Rev.1.05a: Updated Pin Description to include DQPn designation 38/38 © 2004, GSI Technology ...

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