MT47H32M8BP-3:B Micron Technology Inc, MT47H32M8BP-3:B Datasheet
MT47H32M8BP-3:B
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MT47H32M8BP-3:B Summary of contents
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... Revision Note: Data Rate (MT/ 400 533 400 533 400 400 1 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM 1 ≤ 85°C) C ≤ 95°C; C ≤ 85°C) A ≤ 105° Not all options listed can be combined to define an offered product ...
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... Table 2: Addressing Parameter Configuration 16 Meg banks Refresh count Row address Bank address Column address Figure 1: 256Mb DDR2 Part Numbers Example Part Number: MT47H32M8BP-3 :B MT47H Configuration Configuration 64 Meg x 4 64M4 32 Meg x 8 32M8 16 Meg x 16 16M16 Package Pb-free 84-ball 8mm x 14mm FBGA ...
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... DLL Enable/Disable ................................................................................................................................... 76 Output Drive Strength ................................................................................................................................ 76 DQS# Enable/Disable ................................................................................................................................. 76 RDQS Enable/Disable ................................................................................................................................. 76 Output Enable/Disable ............................................................................................................................... 76 On-Die Termination (ODT) ........................................................................................................................ 77 PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM 3 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
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... CKE Low Anytime ...................................................................................................................................... 120 ODT Timing .................................................................................................................................................. 122 MRS Command to ODT Update Delay ........................................................................................................ 124 PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM 4 Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
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... Table 39: Minimum Delay with Auto Precharge Enabled ................................................................................. 68 Table 40: Burst Definition .............................................................................................................................. 72 Table 41: READ Using Concurrent Auto Precharge ......................................................................................... 93 Table 42: WRITE Using Concurrent Auto Precharge ........................................................................................ 99 Table 43: Truth Table – CKE ......................................................................................................................... 114 PDF: 09005aef8117c187 256MbDDR2.pdf - Rev DS, DH Derating Values with Differential Strobe ............................................ 256Mb: x4, x8, x16 DDR2 SDRAM and IH) ................................................... and IH) .......................................... and DH ...
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... Figure 47: READ Interrupted by READ ........................................................................................................... 91 Figure 48: READ-to-WRITE ............................................................................................................................ 91 Figure 49: READ-to-PRECHARGE – ...................................................................................................... 92 Figure 50: READ-to-PRECHARGE – ...................................................................................................... 92 PDF: 09005aef8117c187 256MbDDR2.pdf - Rev .............................................................................................................. .............................................................................................................. ............................................................................................................. ............................................................................................................ 61 t RCD (MIN) .............................................................................. 85 6 256Mb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef8117c187 256MbDDR2.pdf - Rev DQSQ, QH, and Data Valid Window .................................................. DQSQ, QH, and Data Valid Window ...................................................... and DQSCK .......................................................................................... 98 7 256Mb: x4, x8, x16 DDR2 SDRAM Micron Technology, Inc. reserves the right to change products or specifications without notice. ©2003 Micron Technology, Inc. All rights reserved. ...
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... Bank active READ WRITE PRE, PRE_A Precharging identify all timing requirements or possible command restrictions such as multibank in- teraction, power down, entry/exit, etc. 8 256Mb: x4, x8, x16 DDR2 SDRAM State Diagram CKE_L Self refreshing REFRESH Refreshing Precharge power- down CKE_L ACT = ACTIVATE ...
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... I/O balls. A bidirectional data strobe (DQS, DQS#) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR2 SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte (LDQS, LDQS#) and one for the upper byte (UDQS, UDQS#). The DDR2 SDRAM operates from a differential clock (CK and CK#) ...
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... Any specific requirement takes precedence over a general statement. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM Functional Description 10 Micron Technology, Inc. reserves the right to change products or specifications without notice. exceeds C is < ...
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... Functional Block Diagrams The DDR2 SDRAM is a high-speed CMOS, dynamic random access memory inter- nally configured as a multibank DRAM. Figure 3: 64 Meg x 4 Functional Block Diagram ODT Control CKE logic CK CK# CS# RAS# CAS# WE# Refresh 13 Row- Mode counter registers address MUX 15 13 ...
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... FIFO logic 128 64 and (x64) drivers Internal Column CK out CK, CK# Column- decoder address 2 counter/ latch Column 0, Column 1 12 256Mb: x4, x8, x16 DDR2 SDRAM Functional Block Diagrams ODT control V dd CK, CK# sw1 sw2 sw3 DLL sw1 sw2 sw3 8 MUX DRVRS Data ...
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... NF, RDQS#/ DM, DM/RDQS V SSQ DQ1 V DDQ V DQ3 SSQ V V REF SS CKE WE# BA0 BA1 A10 A12 RFU 13 256Mb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions DQS#/NU V SSQ DDQ DQS V NF, DQ7 SSQ V DQ0 V DDQ DDQ DQ2 V NF, DQ5 SSQ SSDL DD RAS# ...
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... DQ1 DDQ DQ3 V SSQ V V REF SS CKE WE# BA0 BA1 A10 A12 RFU 14 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM UDQS#/NU V SSQ DDQ UDQS V DQ15 SSQ V DQ8 V DDQ DDQ DQ10 V DQ13 SSQ V ...
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... Input On-die termination: ODT enables (registered HIGH) and disables (registered LOW) termina- tion resistance internal to the DDR2 SDRAM. When enabled, ODT is only applied to each of the following balls for the x4 configuration: DQ[3:0], DQS, DQS#, and DM; for the x8 config- uration: DQ[7:0], DQS, DQS#, RDQS, RDQS#, and DM; and for the x16 configuration: DQ[15:0], LDM, UDM, LDQS, LDQS#, UDQS, and UDQS# ...
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... Not Used: If EMR(E10 For the x16 configuration UDQS# and E8 = LDQS#. If EMR(E10 For the x16 configuration and E8 = NU. – RFU Reserved for future use: Bank address BA2, row address bits A[15:13]. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM Ball Assignments and Descriptions /2). DDQ and ...
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... Ball A1 ID TYP C L 11.2 14.0 ±0. 6.4 8.0 ±0.15 17 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM Packaging 0.25 MIN Ball A1 ID location 1.2 MAX ©2003 Micron Technology, Inc. All rights reserved. ...
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... TYP Ball A1 ID 12.0 ±0. 8 6.4 8.0 ±0.15 18 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM Packaging 0.25 MIN Ball A1 ID location 1.2 MAX ©2003 Micron Technology, Inc. All rights reserved. ...
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... PDF: 09005aef8117c187 256MbDDR2.pdf - Rev +1.8V ±0.1V MHz 25° / OUT(DC) DDQ with I/O balls, reflecting the fact that they are matched in loading. any given device. 19 256Mb: x4, x8, x16 DDR2 SDRAM Symbol Min Max Units Notes C 1.0 CK – C 0.25 DCK C 1.0 I – C ...
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... TN-00-08, “Thermal Applications,” prior to using the thermal impedances listed in Table 7. For designs that are expected to last several years and require the flexi- bility to use several DRAM die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size re- duction. The DDR2 SDRAM device’ ...
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... Figure 10. This case temperature limit is allowed to be exceeded briefly during pack- age reflow, as noted in Micron technical note TN-00-15, “Recommended Soldering Parameters.” in Figure 10. Length (L) 0.5 (L) 0.5 (W) Width (W) Lmm x Wmm FBGA 21 256Mb: x4, x8, x16 DDR2 SDRAM Min Max Units T –55 150 STG T 0 ...
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... Airflow = 0m/s Airflow = 1m/s 59.0 46.7 37.8 32.5 53.6 40.0 36.6 29 viewed as a typical number. 22 256Mb: x4, x8, x16 DDR2 SDRAM θ JA (°C/W) θ JB (°C/W) Airflow = 2m/s 43.1 25.0 30.7 20.5 35.2 20.0 27.5 19 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... Defined by pattern in Table 9 Defined by pattern in Table 9 Timing Patterns (4-Bank Interleave READ Operation) DD7 I Timing Patterns DD7 -3 A0 RA0 RA1 RA2 RA3 -37E A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 -5E A0 RA0 A1 RA1 A2 RA2 A3 RA3 256Mb: x4, x8, x16 DDR2 SDRAM DD -37E - 7.5 7 3.75 5 ...
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... DD I DD2P I DD2Q I DD2N I DD3Pf I DD3Ps I DD3N DD4W ), DD4R ), 256Mb: x4, x8, x16 DDR2 SDRAM DD -3 -37E x4 x16 90 80 x4, x8 100 90 x16 100 90 x4, x8, x16 x16 x16 40 35 Fast PDN exit 30 25 MR12 = 0 Slow PDN exit 6 6 MR12 = 1 x4 x16 ...
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... DD0 DD1 DD2N DD2Q ≥ 85° 2%; I must be derated by 20 DD2P 30%; and I must be derated by 80% (I DD6 T < 85°C and the 2X refresh option is still enabled 256Mb: x4, x8, x16 DDR2 SDRAM Configuration -3 -37E x4, x8 180 170 x16 180 170 x4, x8, x16 x4, x8 250 ...
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AC Timing Operating Specifications Table 11: AC Operating Specifications and Conditions Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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Table 11: AC Operating Specifications and Conditions (Continued) Not all speed grades listed may be supported for this device; refer to the title page for speeds supported; Notes: 1–5 apply to the entire table +1.8V ±0.1V ...
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... Micron requires less derating by allowing t vice output is no longer driving ( RPST) or beginning to drive ( 34 256Mb: x4, x8, x16 DDR2 SDRAM AC Timing Operating Specifications -to-V swing 1.0V in the test environment and V . Slew rates other than 1.0 V/ns may ...
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... The inputs to the DRAM must be aligned to the associated clock, that is, the actual clock 19. The DRAM output timing is aligned to the nominal or average clock. Most output param- 20. When DQS is used single-ended, the minimum limit is reduced by 100ps. 21. 22. 23. This is not a device limit. The device will operate with a negative value, but system per- 24 recommended that DQS be valid (HIGH or LOW before the WRITE command. 25. The intent of the “ ...
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... READ command internally latches the READ so that data will output CL later. This parameter is only applicable when t t 533 MHz when RTP = 7.5ns. If RTP/(2 × (MIN) has to be satisfied as well. The DDR2 SDRAM will automatically delay the internal t PRECHARGE command until RAS (MIN) has been satisfied ...
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... V . This measurement taken at the nearest V REF(DC) is not applied directly to the device resistors, is expected to be set equal REF 37 256Mb: x4, x8, x16 DDR2 SDRAM AC and DC Operating Conditions t AON (MAX) is when the ODT resistance is fully on. t ERR 5per t ERR t AC (MAX) + 1000 but it will likely be ...
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... Measure voltage (VM) at tested ball with no load. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev DDQ and R are determined by separately applying V TT1(EFF) TT2(EFF) being tested, and then measuring current, I(V between –40°C and 0° 256Mb: x4, x8, x16 DDR2 SDRAM ODT DC Electrical Characteristics Symbol Min Nom Max TT1(EFF) R 120 150 ...
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... Note: PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN Input Electrical Characteristics and Operating Conditions Symbol V V IH(DC) V IL(DC) + 300mV allowed provided 1.9V is not exceeded. DDQ Symbol 256Mb: x4, x8, x16 DDR2 SDRAM Min Max 1 + 125 V REF(DC) DDQ –300 V - 125 REF(DC) Min Max V + 250 V IH(AC) ...
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... DQS) level and V is expected to be approximately 0.5 × 300mV allowed provided 1.9V is not exceeded. DDQ X X RDQS#, LDQS#, and UDQS# signals. V /2. DDQ ID(DC)min 40 256Mb: x4, x8, x16 DDR2 SDRAM Max V DDQ V DDQ V DDQ - 175 0.50 × 175 DDQ ...
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... Numbers in diagram reflect nominal values (V PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN Input Electrical Characteristics and Operating Conditions 41 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM = 1.8V). DDQ ©2003 Micron Technology, Inc. All rights reserved. ...
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... SSTL_18 receiver. The actual current val- IL,max ues are derived by shifting the desired driver operating point (see output IV curves) along a 21Ω load line to define a convenient driver current for measurement. 42 256Mb: x4, x8, x16 DDR2 SDRAM Max - 125 0.50 × 125 ...
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... V teed by design and characterization. 40°C and 0° DDQ 25Ω Reference point ) 43 256Mb: x4, x8, x16 DDR2 SDRAM Nom Max – 4 – +1.8V ±0.1V +1.8V ±0.1V. DDQ DD must be less than 23.4Ω for values of V must be less than 23.4Ω for values ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 5.63 11.30 16.52 22.19 27.59 32.39 36.45 40.38 44.01 47.01 49.63 51.71 53.32 54 ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 –5.63 –11.30 –16.52 –22.19 –27.59 –32.39 –36.45 –40.38 –44.01 –47.01 –49.63 –51.71 –53.32 – ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 2.98 5.99 8.75 11.76 14.62 17.17 19.32 21.40 23.32 24.92 26.30 27.41 28.26 29 ...
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... DDR2 SDRAM Output Driver Characteristics 1.5 Nom 0.00 –2.98 –5.99 –8.75 –11.76 –14.62 –17.17 –19.32 –21.40 –23.32 –24.92 –26.30 –27.41 –28.26 – ...
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... Voltage Across Clamp (V) 48 256Mb: x4, x8, x16 DDR2 SDRAM Minimum Ground Clamp Current (mA) 0.0 0.0 0.0 0.0 0.0 ...
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... Figure 20) 0.19 Vns DDQ (see Figure 21) 0.19 Vns SSQ Maximum amplitude DDQ SSQ Time (ns) SSQ Maximum amplitude Time (ns) 49 256Mb: x4, x8, x16 DDR2 SDRAM Specification -25/-25E -3/-3E 0.50V 0.50V 0.50V 0.50V 0.50V 0.50V 0.66 Vns 0.80 Vns 0.66 Vns 0.80 Vns ...
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... AC level: 2 × × V IL(DC the falling edge. For example, the CK/CK# would be –250mV to +500mV for IH(DC) CK rising edge and would be +250mV to –500mV for CK falling edge. 50 256Mb: x4, x8, x16 DDR2 SDRAM Min Max Units See Note 2 See Note 5 V × 0.49 V × ...
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... REF(DC) level is used for the derating value (Figure 25 (page 55)). REF(DC the time of the rising clock transition), a valid IH[AC] IL[AC] 51 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating t IH (hold time) required is calculated IH (base) value to the Δ IS and Δ (base) + Δ ...
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... PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating and IH) CK, CK# Differential Slew Rate 2.0 V/ns 1.5 V/ns Δ Δ Δ Δ ...
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... DDR2 SDRAM Input Slew Rate Derating and IH) 1.0 V/ns Δ Δ +210 +154 +203 +149 +193 +143 +180 ...
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... IL(AC)max = rising signal Δ REF Nominal region line Tangent line Nominal line ΔTF SS Setup slew rate = rising signal 54 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region Δ IH(AC)min REF(DC) = Δ Tangent line REF region ΔTR ...
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... DDQ REF region Tangent line Nominal V SS ΔTR Tangent line ( Hold slew rate REF[DC] IL[DC]max = falling signal ΔTR 55 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region Δ Nominal line Tangent line REF line region ΔTF ...
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... AC/DC trip points to DQ referenced to V Table 35 (page 59). Table 34 provides the and DH ) for DDR2-533. Table 35 provides the the and DH ) for DDR2-400 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.4 V/ns 1.2 V/ns 1.0 V/ns Δ Δ Δ Δ Δ – ...
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... Converting the derated base values from DQ referenced the AC/DC trip points to DQ referenced to V ble 33 provides the V -based fully derated values for the DQ ( REF 57 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating 1.4 V/ns 1.2 V/ns 1.0 V/ns Δ Δ Δ ...
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... DDR2 SDRAM Input Slew Rate Derating and and DH -specified values REF 1.0 V/ns 0.8 V/ns 0.6 V/ns ...
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... Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating ) at DDR2-533 REF ) REF 1.0 V/ns 0.8 V/ns 0.6 V/ ...
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... Tangent line Tangent line Nominal line ΔTF ΔTR Tangent line ( Tangent line (V REF[DC] IL[AC]max Setup slew rate = = rising signal ΔTF 60 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region IH(AC)min REF(DC) = ΔTR and V IL(DC)max IH(DC)min ...
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... IS DDQ REF region Tangent line Nominal V SS ΔTR Tangent line ( REF[DC] IL[DC]max Hold slew rate = ΔTR falling signal 61 256Mb: x4, x8, x16 DDR2 SDRAM Input Slew Rate Derating Nominal slew rate REF region Δ IH(DC)min REF(DC) = ΔTF and V IL(DC)max IH(DC)min Nominal ...
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... Figure 30: AC Input Test Signal Waveform Command/Address Balls Logic levels V levels REF Figure 31: AC Input Test Signal Waveform for Data with DQS, DQS# (Differential) Logic levels V levels REF PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM CK DQS# DQS t DS ...
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... Figure 32: AC Input Test Signal Waveform for Data with DQS (Single-Ended) Logic levels V levels REF Figure 33: AC Input Test Signal Waveform (Differential PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM DQS DDQ Crossing point Vswing SSQ 63 Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
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... H Power-down exit L 1. All DDR2 SDRAM commands are defined by states of CS#, RAS#, CAS#, WE#, and CKE at Notes: 2. The state of ODT does not affect the states described in this table. The ODT function is 3. “X” means “H or L” (but a defined logic level) for valid I 4. BA2 is only applicable for densities ≥ ...
Page 65
... Issue DESELECT or NOP commands, or allowable commands to the other bank, on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and this table, and according to Table 38 (page 67). 65 256Mb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any READ burst is com- t RCD has been met ...
Page 66
... NOP commands must be applied on each positive clock edge during these states): Refresh: Starts with registration of a REFRESH command and ends when t met. After RFC is met, the DDR2 SDRAM will be in the all banks idle state. Accessing Starts with registration of the LOAD MODE command and ends when t mode MRD has been met ...
Page 67
... A READ burst has been initiated with auto precharge disabled and has not yet terminated. Write: A WRITE burst has been initiated with auto precharge disabled and has not yet terminated. 67 256Mb: x4, x8, x16 DDR2 SDRAM Command/Action t RP has been met, and any READ t RCD has been met. ...
Page 68
... WRITE or WRITE with auto precharge DESELECT The DESELECT function (CS# HIGH) prevents new commands from being executed by the DDR2 SDRAM. The DDR2 SDRAM is effectively deselected. Operations already in progress are not affected. DESELECT is also referred to as COMMAND INHIBIT. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN ...
Page 69
... If auto precharge is selected, the row being accessed will be pre- charged at the end of the WRITE burst; if auto precharge is not selected, the row will remain open for subsequent accesses. DDR2 SDRAM also supports the AL feature, which allows a READ or WRITE command to be issued prior to command to the internal device by AL clock cycles. ...
Page 70
... Mode Register (MR) The mode register is used to define the specific mode of operation of the DDR2 SDRAM. This definition includes the selection of a burst length, burst type, CAS latency, operat- ing mode, DLL RESET, write recovery, and power-down mode, as shown in Figure 34 (page 71) ...
Page 71
... Burst Length Burst length is defined by bits M0–M2, as shown in Figure 34. Read and write accesses to the DDR2 SDRAM are burst-oriented, with the burst length being programmable to either four or eight. The burst length determines the maximum number of column loca- tions that can be accessed for a given READ or WRITE command. ...
Page 72
... Figure 34 (page 71). When bit M7 is “1,” no other bits of the mode register are programmed. Programming bit M7 to “1” places the DDR2 SDRAM into a test mode that is only used by the manufacturer and should not be used. No operation or functionality is guaranteed if M7 bit is “1.” ...
Page 73
... Write Recovery Write recovery (WR) time is defined by bits M9–M11, as shown in Figure 34 (page 71). The WR register is used by the DDR2 SDRAM during WRITE with auto precharge opera- tion. During WRITE with auto precharge operation, the DDR2 SDRAM delays the inter- nal auto precharge operation by WR clocks (programmed in bits M9–M11) from the last data burst. An example of WRITE with auto precharge is shown in Figure 63 (page 106). WR values clocks may be used for programming bits M9– ...
Page 74
... DDR2 SDRAM also supports a feature called posted CAS additive latency (AL). This fea- ture allows the READ command to be issued prior to internal command to the DDR2 SDRAM by AL clocks. The AL feature is described in further detail in Posted CAS Additive Latency (AL) (page 77). Examples and are shown in Figure 35; both assume READ command is registered at clock edge n, and the clocks, the data will be available nominally coincident with clock edge (this assumes ...
Page 75
... OCD operation, all three bits must be set to “1” for the OCD default state, then set to “0” before initialization is finished. 75 256Mb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) t MRD before initiating any subsequent opera- ...
Page 76
... The output disable feature is intended to be used during I characterization of read current. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev DQSCK parameters. 76 Micron Technology, Inc. reserves the right to change products or specifications without notice. 256Mb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR) ©2003 Micron Technology, Inc. All rights reserved. DD ...
Page 77
... In this operation, the DDR2 SDRAM allows a READ or WRITE command to be issued prior to using this feature would set held for the time of the AL before it is issued internally to the DDR2 SDRAM device controlled by the sum of AL and CL CL. WRITE latency (WL) is equal to RL minus one clock × ...
Page 78
... ACTIVE n WRITE n Command DQS, DQS Notes PDF: 09005aef8117c187 256MbDDR2.pdf - Rev NOP NOP NOP AC, DQSCK, and T2 T3 NOP NOP t RCD (MIN 256Mb: x4, x8, x16 DDR2 SDRAM Extended Mode Register (EMR NOP NOP NOP Transitioning Data t DQSQ NOP NOP NOP Transitioning Data Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 79
... Extended mode register (EMR2) Extended mode register (EMR3) grammed to “0.” served for future use and must be programmed to “0.” 79 256Mb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 2 (EMR2) t MRD before initiating any subsequent opera Address bus ...
Page 80
... Extended mode register (EMR) Extended mode register (EMR2) Extended mode register (EMR3) programmed to “0.” served for future use and must be programmed to “0.” 80 256Mb: x4, x8, x16 DDR2 SDRAM Extended Mode Register 3 (EMR3) t MRD before initiating any subsequent opera Address bus ...
Page 81
... Initialization DDR2 SDRAM must be powered up and initialized in a predefined manner. Operational procedures other than those specified may result in undefined operation. Figure 41 (page 82) illustrates, and the notes outline, the sequence required for power-up and initialization. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev. M 7/09 EN 256Mb: x4, x8, x16 DDR2 SDRAM 81 Micron Technology, Inc ...
Page 82
Figure 41: DDR2 Power-Up and Initialization DDL V VTD 1 DDQ REF Tb0 T0 Ta0 LVCMOS SSTL_18 2 low level 2 CKE low level ...
Page 83
... TT to the ODT ball (all other inputs may be undefined; I/Os and outputs must be less than V during voltage ramp time to avoid DDR2 SDRAM device latch-up). V DDQ plied directly to the device; however, least one of the following two sets of conditions ( must be met to obtain a stable ...
Page 84
... Issue a LOAD MODE command to the EMR to enable OCD default by setting bits E7, E8, 13. Issue a LOAD MODE command to the EMR to enable OCD exit by setting bits E7, E8, and 14. The DDR2 SDRAM is now initialized and ready for normal operation 200 clock cycles af- 15. DM represents DM for the x4, x8 configurations and UDM, LDM for the x16 configura- 16 ...
Page 85
... ACTIVATE Before any READ or WRITE commands can be issued to a bank within the DDR2 SDRAM, a row in that bank must be opened (activated), even when additive latency is used. This is accomplished via the ACTIVATE command, which selects both the bank and the row to be activated. ...
Page 86
... READ Row Col Row Col Bank b Bank b Bank c Bank c t FAW (MIN 3.75ns FAW (MIN) = 37.5ns. 86 256Mb: x4, x8, x16 DDR2 SDRAM ACT READ NOP NOP Row Col Bank d Bank d t RRD (MIN) = 7.5ns, Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 87
... READ burst as long as the interruption occurs on a 4-bit boundary due to the 4n prefetch architecture of DDR2 SDRAM. As shown in Figure 47 (page 91), READ burst operations may not be interrupted or truncated with any other command except another READ com- mand ...
Page 88
... READ NOP NOP Bank a, Col ( READ NOP NOP Bank a, Col ( AC, DQSCK, and 88 256Mb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 T4n NOP NOP T4n NOP NOP T3n T4 T4n NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 89
... READ Bank, Bank, Col n Col b t CCD READ NOP READ Bank, Bank, Col n Col b t CCD AC, DQSCK, and 89 256Mb: x4, x8, x16 DDR2 SDRAM T5n T3 T3n T4 T4n T5 NOP NOP NOP T5n T2n T3 T3n T4 T4n T5 NOP NOP NOP DO n Transitioning Data t DQSQ. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 90
... NOP READ Bank, Bank, Col n Col READ NOP NOP READ Bank, Bank, Col n Col AC, DQSCK, and tive READs. 90 256Mb: x4, x8, x16 DDR2 SDRAM T3n T4 T4n T5 T6 T6n T7 NOP NOP NOP NOP T4n T5 T5n NOP NOP NOP NOP DO n Transitioning Data t DQSQ. ...
Page 91
... T2 can be either same bank or different bank). terrupting READ command NOP NOP WRITE AC, DQSCK, and t RTP is the minimum time from the rising clock edge that initiates the last 4-bit 91 256Mb: x4, x8, x16 DDR2 SDRAM Valid Valid Valid Transitioning Data t CK from previous READ. ...
Page 92
... READ NOP NOP NOP AL + BL/2 - 2CK + MAX ( t RTP 2CK) Bank ≥t RAS (MIN) ≥t RC (MIN) t RTP ≥ 2 clocks AC, DQSCK, and 92 256Mb: x4, x8, x16 DDR2 SDRAM NOP NOP ACT Bank a Valid ≥ (MIN) Transitioning Data Don’t Care t DQSQ NOP PRE ...
Page 93
... READ with Auto Precharge If A10 is high when a READ command is issued, the READ with auto precharge function is engaged. The DDR2 SDRAM starts an auto precharge operation on the rising clock edge that (BL/2) cycles later than the read with auto precharge command provi- t ded edge, the start point of the auto precharge operation will be delayed until satisfied ...
Page 94
... CK NOP 1 NOP 1 READ 2 Col n 5 Bank x t RCD RAS these times. but to when the device begins to drive or no longer drives, respectively. order. 94 256Mb: x4, x8, x16 DDR2 SDRAM T7n T8 NOP 1 PRE 3 NOP 1 NOP 1 t RTP 4 All banks One bank Bank DQSCK (MIN) ...
Page 95
... NOP commands are shown for ease of illustration; other commands may be valid at Notes ( the case shown. 3. The DDR2 SDRAM internally delays auto precharge until both 4. Enable auto precharge. 5. I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level data-out from column n; subsequent elements are applied in the programmed PDF: 09005aef8117c187 256MbDDR2 ...
Page 96
... DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. T2 and at T2n are “early DQS,” are “nominal DQS,” and at T3n are “late DQS.” derived from HP 256Mb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n DQSQ 2 t DQSQ 2 t DQSQ ...
Page 97
... CH clock transitions collectively when a bank is active. t DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS transitions, and ends with the last valid transition of DQ. lower byte, and UDQS defines the upper byte. 97 256Mb: x4, x8, x16 DDR2 SDRAM T3 T3n ...
Page 98
... I/O balls, when entering or exiting High-Z, are not referenced to a specific voltage level, WRITE WRITE bursts are initiated with a WRITE command. DDR2 SDRAM uses WL equal to RL minus one clock cycle ( 1CK) (see READ (page 69)). The starting column and bank addresses are provided with the WRITE command, and auto precharge is either enabled or disabled for that access ...
Page 99
... WRITE burst as long as the interruption occurs on a 4-bit boundary due to the 4n-prefetch architec- ture of DDR2 SDRAM. WRITE burst operations may not be interrupted or truncated with any command except another WRITE command, as shown in Figure 59 (page 102). ...
Page 100
... Rev CK# CK WRITE NOP Bank a, Col b WL ± t DQSS DQSS DQSS 100 256Mb: x4, x8, x16 DDR2 SDRAM T2 T2n T3 T3n T4 NOP NOP NOP DQSS DQSS Transitioning Data Don’t Care t DQSS. Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 101
... Bank, Bank, Col b Col n WL ± DQSS CK# CK WRITE NOP NOP Bank, Col b WL ± t DQSS 101 256Mb: x4, x8, x16 DDR2 SDRAM T2n T3 T3n T4 T4n T5 T5n NOP NOP NOP Transitioning Data t DQSS. T2n T3 T3n T4 T4n T5 T5n WRITE NOP NOP Bank, Col n ...
Page 102
... NOP 2 Valid 5 Valid issued to banks used for WRITEs at T0 and T2. starts with T7 and not T5 (because from MR and not the truncated length and T2 can be either same bank or different bank). terrupting WRITE command. 102 256Mb: x4, x8, x16 DDR2 SDRAM NOP 2 NOP 2 Valid 4 Valid ...
Page 103
... WTR is required for any READ following a WRITE to the same device, but it is not re- quired between module ranks. t WTR is referenced from the first positive CK edge after the last data-in pair. greater. 103 256Mb: x4, x8, x16 DDR2 SDRAM NOP READ NOP NOP ...
Page 104
... referenced from the first positive CK edge after the last data-in pair. and WRITE commands may be to different banks, in which case the PRECHARGE command could be applied earlier. 104 256Mb: x4, x8, x16 DDR2 SDRAM NOP NOP NOP t WR Transitioning Data t DQSS not required and Micron Technology, Inc. reserves the right to change products or specifications without notice. © ...
Page 105
... Bank x t RCD ± t DQSS (NOM) these times DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 105 256Mb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS 5 t DQSL t DQSH t WPST ...
Page 106
... WL ± t DQSS (NOM) t WPRE these times. rounding up to the next integer value DSH is applicable during DQSS (MIN) and is referenced from T6 DSS is applicable during DQSS (MAX) and is referenced from T7. 106 256Mb: x4, x8, x16 DDR2 SDRAM T5 T5n T6 T6n T7 T8 NOP 1 NOP 1 NOP 1 NOP RAS ...
Page 107
... WR starts at the end of the data burst regardless of the data mask condition DSH is applicable during DQSS (MIN) and is referenced from T7 DSS is applicable during DQSS (MAX) and is referenced from T8. 107 256Mb: x4, x8, x16 DDR2 SDRAM T9 T6 T6n T7 T7n T8 NOP 1 NOP 1 NOP RAS ...
Page 108
... DSH (MIN) generally occurs during t DSS (MIN) generally occurs during t RP timing applies. When the PRECHARGE (ALL) com- t RPA timing applies, regardless of the number of banks opened. 108 256Mb: x4, x8, x16 DDR2 SDRAM T3 T3n T4 t DSS 2 t DSH 1 t DSS DQSL t DQSH ...
Page 109
... REFRESH The commercial temperature DDR2 SDRAM requires REFRESH cycles at an average in- terval of 7.8125µs (MAX) and all rows in all banks must be refreshed at least once every 64ms. The refresh period begins when the REFRESH command is registered and ends t RFC (MIN) later. The average interval must be reduced to 3.9µs (MAX) when T ceeds +85° ...
Page 110
... First, the differential clock must be stable and meet prior to CKE going back to HIGH. Once CKE is HIGH ( with three clock registrations), the DDR2 SDRAM must have NOP or DESELECT com- mands issued for ments is used to apply NOP or DESELECT commands for 200 clock cycles before applying any other command ...
Page 111
... XSNR is required before any nonREAD command can be applied. off ( TT ing self refresh at state T1. t XSRD (200 cycles of CK) is required before a READ command can be applied at state Td0. refresh. 111 256Mb: x4, x8, x16 DDR2 SDRAM Tb0 Tc0 Ta2 t ISXR 2 t CKE 3 NOP 4 NOP 4 ...
Page 112
... Figure 69 (page 115)–Figure 76 (page 118). Table 43 (page 114) is the CKE Truth Table. DDR2 SDRAM requires CKE to be registered HIGH (active) at all times that an access is in progress—from the issuing of a READ or WRITE command until completion of the burst. Thus, a clock suspend is not supported. For READs, a burst completion is defined when the read postamble is satisfied ...
Page 113
... XARDS timing is used for exit active power-down to READ command if slow exit is selec- ted via MR (bit 12 = 1). the DLL was not in a locked state when CKE went LOW, the DLL must be reset after exiting power-down mode for proper READ operation. 113 256Mb: x4, x8, x16 DDR2 SDRAM Power-Down Mode ...
Page 114
... CKE (n) is the logic state of CKE at clock edge n; CKE ( was the state of CKE at the Notes: 2. Current state is the state of the DDR2 SDRAM immediately prior to clock edge n. 3. Command (n) is the command registered at clock edge n, and action ( result of 4. The state of ODT does not affect the states described in this table. The ODT function is 5. Power-down modes do not perform any REFRESH operations. The duration of power- 6. “ ...
Page 115
... Power-down or self refresh entry may occur after the READ burst completes. PDF: 09005aef8117c187 256MbDDR2.pdf - Rev NOP NOP Valid entry NOP NOP entry is at T6. 115 256Mb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid DO DO Power-down 2 or self refresh entry Transitioning Data NOP 1 Valid Valid DO DO ...
Page 116
... NOP NOP Valid cur later at Ta1, prior to RP being satisfied next integer CK. 116 256Mb: x4, x8, x16 DDR2 SDRAM Power-Down Mode NOP 1 Valid Valid t WTR Power-down or self refresh entry 1 Transitioning Data T5 Ta0 Ta1 Valid 1 Valid NOP WR 2 Power-down or self refresh entry Indicates a break in ...
Page 117
... REFRESH REFRESH command. Precharge power-down entry occurs prior to fied Valid ACT VALID VATE command. Active power-down entry occurs prior to 117 256Mb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN) Power-down 1 entry Don’t Care t RFC (MIN) being satis NOP ...
Page 118
... PRE Valid All banks A10 vs Single bank CKE 1 x PRECHARGE command. Precharge power-down entry occurs prior to isfied Valid LM Valid 118 256Mb: x4, x8, x16 DDR2 SDRAM Power-Down Mode T2 T3 NOP t CKE (MIN Power-down 1 entry Don’t Care NOP NOP t CKE (MIN) t MRD ...
Page 119
... Precharge Power-Down Clock Frequency Change When the DDR2 SDRAM is in precharge power-down mode, ODT must be turned off and CKE must logic LOW level. A minimum of two differential clock cycles must pass after CKE goes LOW before clock frequency may change. The device input clock frequency is allowed to change only within minimum and maximum operating frequen- cies specified for the particular speed grade ...
Page 120
... If CKE asynchronously drops LOW during any valid operation (including a READ or WRITE burst), the memory controller must satisfy the timing parameter turning off the clocks. Stable clocks must exist at the CK, CK# inputs of the DRAM be- fore CKE is raised HIGH, at which time the normal initialization sequence must occur (see Initialization) ...
Page 121
... V must be valid at all times. DD DDL DDQ TT REF represents DQS, DQS#, UDQS, UDQS#, LDQS, LDQS#, RDQS, and RDQS# for the appropri- ate configuration (x4, x8, x16). completion of the burst. 121 256Mb: x4, x8, x16 DDR2 SDRAM T5 Ta0 CKE (MIN) 1 NOP 2 4 High-Z High-Z ...
Page 122
... AXPD (MIN) is not satisfied because ODT LOW occurs at state Ta0 AXPD (MIN) is not satisfied, AOFPD timing parameters apply. t AXPD (MIN) is satisfied, 122 256Mb: x4, x8, x16 DDR2 SDRAM t AOF timing parameters are applied, as shown t AOFPD timing parameters apply. t AONPD timing parameters apply. t ...
Page 123
... Active power-down slow (asynchronous) Precharge power-down (asynchronous AOND/ AOFD (synchronous AONPD/ AOFPD (asynchronous) 123 256Mb: x4, x8, x16 DDR2 SDRAM Synchronous t t AXPD (8 CKs) First CKE latched HIGH Any mode except self refresh mode t AOND/ Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 124
... MOD window until Valid Valid Valid Valid Valid Valid t AOND TT t AON (MIN) t AON (MAX) 124 256Mb: x4, x8, x16 DDR2 SDRAM t MOD (MAX) updates the R setting. TT Ta2 Ta3 Ta4 NOP NOP NOP 2 t MOD t IS Undefined New setting Indicates a break in time scale t MOD is met ...
Page 125
... Valid Valid Valid Valid Valid Valid t AONPD (MAX) t AONPD (MIN) t AOFPD (MIN) Transitioning NOP NOP NOP TT TT Transitioning R TT 125 256Mb: x4, x8, x16 DDR2 SDRAM Valid Valid Valid Valid Valid Valid Valid Valid t AOFPD (MAX) R Unknown NOP NOP NOP t ANPD (MIN) ...
Page 126
... CK# CK Command CKE ODT R ODT R PDF: 09005aef8117c187 256MbDDR2.pdf - Rev NOP NOP NOP TT TT Transitioning R TT 126 256Mb: x4, x8, x16 DDR2 SDRAM NOP NOP NOP NOP t ANPD (MIN) t AOND t AON (MAX) t AON (MIN) t AONPD (MAX) t AONPD (MIN) R Unknown Micron Technology, Inc. reserves the right to change products or specifications without notice. ...
Page 127
... PDF: 09005aef8117c187 256MbDDR2.pdf - Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break in R Unknown TT time scale 127 256Mb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOFD t AOF (MIN) t AOFPD (MAX) t AOFPD (MIN Transitioning Micron Technology, Inc ...
Page 128
... Rev Ta0 NOP NOP NOP NOP t AXPD (MIN) Indicates a break time scale times occur. 128 256Mb: x4, x8, x16 DDR2 SDRAM Ta1 Ta2 Ta3 Ta4 NOP NOP NOP NOP t AOND t AON (MAX) t AON (MIN) t AONPD (MAX) t AONPD (MIN) Unknown R On ...