FSTUD162450MTD Fairchild Semiconductor, FSTUD162450MTD Datasheet

FSTUD162450MTD

Manufacturer Part Number

FSTUD162450MTD

Description

Manufacturer

Fairchild Semiconductor

Datasheet

1.FSTUD162450MTD.pdf (11 pages)

Specifications of FSTUD162450MTD

Logic Family

FST

Number Of Bits

Technology

CMOS

High Level Output Current

-128mA

Low Level Output Current

128mA

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Operating Supply Voltage (min)

Operating Supply Voltage (typ)

Operating Supply Voltage (max)

5.5V

Pin Count

Mounting

Surface Mount

Lead Free Status / Rohs Status

Compliant

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FSTUD162450GX

(Note 1)

FSTUD162450MTD

FSTUD162450

Configurable 4-Bit to 20-Bit Bus Switch with

and 25

General Description

The Fairchild Universal Bus Switch FSTUD162450 pro-

vides 4-bit, 5-bit, 8-bit, 10-bit, 16-bit, 20-bit of high-speed

CMOS TTL-compatible bus switching. The low On Resis-

tance of the switch allows inputs to be connected to out-

puts without adding propagation delay or generating

additional ground bounce noise.

The FSTUD162450 is designed to allow “customer” config-

uration control of the enable connections. The device can

be organized as either a five 4-bit, four 5-bit, two 10-bit or

one 20-bit bus switch. Also available are 8-bit and 16-bit

enabled configurations (see Functional Description). The

device's bit configuration is controlled through select pin

logic. (see Truth Table). When OE

nected to Port B

The A and B Ports are protected against undershoot to

support an extended range to 2.0V below ground.

Fairchild's

(UHC ) senses undershoot at the I/O and responds by

preventing voltage differentials from developing and turn-

ing the switch on.

Another innovative device feature is the addition of a level

shifting select pin, “S

behaves as a standard N-MOS switch. When S

diode to V

shifting between 5V inputs and 3.3V outputs.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Note 1: BGA package available in Tape and Reel only.

UHC

Order Number

2V Undershoot Protection and Selectable Level Shifting

is a trademark of Fairchild Semiconductor Corporation.

integrated

is integrated into the circuit allowing for level

. When OE

Series Resistors in Outputs

Package Number

”. When S

Preliminary

Undershoot

BGA54A

MTD56

is HIGH, the switch is OPEN.

is LOW, Port A

is LOW, the device

Hardened

54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide

[Tape and Reel]

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

DS500469

is HIGH, a

is con-

Circuit

Features

Applications Note

Select pins S

user configurable control pins. The AC performance of

these pins has not been characterized or tested. Switching

of these select pins during system operation may tempo-

rarily disrupt output logic states and/or enable pin controls.

Undershoot protected to 2V (A and B Ports)

Voltage level shifting

25 switch connection between two ports

Minimal propagation delay through the switch

Low l

Zero bounce in flow-through mode

Control inputs compatible with TTL level

See Applications Notes AN-5008 and AN-5021

for UHC details

Also packaged in plastic Fine-Pitch Ball Grid Array

(FBGA) (Preliminary)

Package Description

, S

are intended to be used as static

April 2001

Revised August 2001

www.fairchildsemi.com

Related parts for FSTUD162450MTD

FSTUD162450MTD Summary of contents

Page 1

... Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide (Note 1) Preliminary [Tape and Reel] FSTUD162450MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. ...

Page 2

Connection Diagrams Pin Assignment for TSSOP Pin Assignment for FBGA (Top Thru View) www.fairchildsemi.com Pin Descriptions Pin Name Description Bus Switch Enables 1 2 1A, 2A Bus A 1B, 2B Bus Bit Configuration ...

Page 3

Logic Diagrams 20-Bit Configuration 5-Bit Configuration 10-Bit Configuration 4-Bit Configuration 3 www.fairchildsemi.com ...

Page 4

Functional Description The device can also be configured and 16-bit device by grounding the unused pins in the 10-bit and 20-bit configu- rations respectively. The 8-bit configuration may also be achieved by connecting two of the 4-bit ...

Page 5

Truth Tables (Continued) 4-Bit Configuration ( Inputs ...

Page 6

Absolute Maximum Ratings Supply Voltage ( Switch Voltage (V ) (Note Input Control Pin Voltage (V ) (Note Input Diode Current ( Output (I ) ...

Page 7

AC Electrical Characteristics Symbol Parameter Propagation Delay Bus-to-Bus PHL PLH (Note Output Enable Time PZH PZL Output Disable Time PHZ PLZ Output ...

Page 8

Undershoot Characteristic Symbol Parameter V Output Voltage During Undershoot OUTU Note 11: This test is intended to characterize the device’s protective capabilities by maintaining output signal integrity during an input transient voltage undershoot event. Device Test Conditions Parameter Value Units ...

Page 9

FIGURE 4. 9 www.fairchildsemi.com ...

Page 10

Physical Dimensions inches (millimeters) unless otherwise noted 54-Ball Fine-Pitch Ball Grid Array (FBGA), JEDEC MO-205, 5.5mm Wide www.fairchildsemi.com Package Number BGA54A Preliminary 10 ...

Page 11

Physical Dimensions Physical Dimensions inches (millimeters) unless otherwise noted (Continued) inches (millimeters) unless otherwise noted (Continued) 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Technology Description The Fairchild Switch family derives from and embodies Fairchild’s proven switch ...

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