74VCX162839MTD Fairchild Semiconductor, 74VCX162839MTD Datasheet

74VCX162839MTD

Manufacturer Part Number

74VCX162839MTD

Description

Manufacturer

Fairchild Semiconductor

Datasheet

1.74VCX162839MTD.pdf (7 pages)

Specifications of 74VCX162839MTD

Logic Family

VCX

Logical Function

Number Of Elements

Number Of Bits

Number Of Inputs

Number Of Outputs

High Level Output Current

-12mA

Low Level Output Current

12mA

Package Type

TSSOP

Propagation Delay Time

9.8ns

Operating Supply Voltage (typ)

1.8/2.5/3.3V

Operating Supply Voltage (max)

3.6V

Operating Supply Voltage (min)

1.65V

Output Type

3-State

Clock-edge Trigger Type

Positive-Edge

Polarity

Non-Inverting

Technology

CMOS

Frequency (max)

250(Min)MHz

Mounting

Surface Mount

Pin Count

Operating Temp Range

-40C to 85C

Operating Temperature Classification

Industrial

Quiescent Current

20uA

Lead Free Status / Rohs Status

Compliant

Current page: 1 of 7
Download datasheet (73Kb)

74VCX162839MTD

74VCX162839

Low Voltage 20-Bit Selectable Register/Buffer

with 3.6V Tolerant Inputs/Outputs

and 26 Series Resistors in the Outputs

General Description

The VCX162839 contains twenty non-inverting selectable

buffered or registered paths. The device can be configured

to operate in a registered, or flow through buffer mode by

utilizing the register enable (REGE) and Clock (CLK) sig-

nals. The device operates in a 20-bit word wide mode. All

outputs can be placed into 3-STATE through use of the OE

pin. These devices are ideally suited for buffered or regis-

tered 168 pin and 200 pin SDRAM DIMM memory mod-

ules.

The 74VCX162839 is designed for low voltage (1.65V to

3.6V) V

The 74VCX162839 is also designed with 26

tors in the outputs. This design reduces line noise in appli-

cations such as memory address drivers, clock drivers, and

bus transceivers/transmitters.

The 74VCX162839 is fabricated with an advanced CMOS

technology to achieve high speed operation while maintain-

ing low CMOS power dissipation.

Ordering Code:

Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.

Logic Symbol

Order Number

applications with I/O compatibility up to 3.6V.

Package Number

MTD56

56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide

series resis-

DS500127

Features

Note 1: To ensure the high-impedance state during power up or power

down, OE should be tied to V

value of the resistor is determined by the current-sourcing capability of the

driver.

Pin Descriptions

Pin Names

CLK

REGE

Compatible with PC100 and PC133 DIMM module

specifications

1.65V–3.6V V

3.6V tolerant inputs and outputs

26 series resistors in the outputs

Power-off high impedance inputs and outputs

Supports live insertion and withdrawal (Note 1)

Static Drive (I

Uses patented noise/EMI reduction circuitry

Latch-up performance exceeds 300 mA

ESD performance:

–I

–O

4.1 ns max for 3.0V to 3.6V V

5.8 ns max for 2.3V to 2.7V V

9.8 ns max for 1.65V to 1.95V V

Human body model

Machine model

12 mA @ 3.0V V

8 mA @ 2.3V V

3 mA @ 1.65V V

(CLK to O

Package Description

)

Output Enable Input (Active LOW)

Inputs

Outputs

Clock Input

supply operation

)

200V

2000V

through a pull-up resistor; the minimum

March 1998

Revised December 2000

Description

www.fairchildsemi.com

Related parts for 74VCX162839MTD

74VCX162839MTD Summary of contents

Page 1

... CMOS power dissipation. Ordering Code: Order Number Package Number 74VCX162839MTD MTD56 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Devices also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code. Logic Symbol © ...

Page 2

Connection Diagram Logic Diagram www.fairchildsemi.com Truth Table Inputs I CLK REGE Logic HIGH L Logic LOW X Don’t Care, ...

Page 3

Absolute Maximum Ratings Supply Voltage ( Input Voltage ( Output Voltage ( Outputs 3-STATE Outputs Active (Note 3) 0. Input Diode Current ( Output ...

Page 4

DC Electrical Characteristics (2.3V Symbol Parameter V HIGH Level Input Voltage IH V LOW Level Input Voltage IL V HIGH Level Output Voltage OH V LOW Level Output Voltage OL I Input Leakage Current I I 3-STATE Output Leakage OZ ...

Page 5

AC Electrical Characteristics Symbol Parameter f Maximum Clock Frequency MAX t Propagation Delay PHL (REGE 0) PLH t Propagation Delay CLK to O PHL n t (REGE 1) PLH Propagation Delay ...

Page 6

AC Loading and Waveforms TEST PLH PHL PZL PLZ PZH PHZ FIGURE 2. Waveform for Inverting and Non-Inverting Functions FIGURE 4. 3-STATE Output Low Enable and Disable Times for Low Voltage ...

Page 7

Physical Dimensions inches (millimeters) unless otherwise noted 56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the ...

Related keywords

74VCX162839MTD datasheet
74VCX162839MTD data sheet
74VCX162839MTD pdf datasheet
74VCX162839MTD component
74VCX162839MTD part
74VCX162839MTD distributor
74VCX162839MTD RoHS
74VCX162839MTD datasheet download