PEB2445NV1.2 Lantiq, PEB2445NV1.2 Datasheet
PEB2445NV1.2
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PEB2445NV1.2 Summary of contents
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ICs for Communications Multipoint Switching and Conferencing Unit - Attenuation MUSAC-A PEB 2445 Version 1.2 Data Sheet 02.96 ...
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PEB 2445 Revision History: Previous Version: Digital Switching and Conferencing IC’s Data Book 01.94 Page Page (in Version (in new 01.94) Version) 220 11 220 11 224, 227, 16, 19, 36 243 249 40 – – ...
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Table of Contents 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table of Contents 6 Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Overview A Complete Family of Efficient Solutions If the issue is digital switching and conferencing, the solution is flexibility, capacity, and economy. Siemens Semiconductor offers the most economical answer to all conceivable applications in this field. Our complete family ...
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The figure below shows the general architecture of a digital exchange. Figure 1 General Exchange Architecture System Background Digital exchanges put calls through by newly arranging the speech signals coded with 8-bit words (PCM time-slots). The code words are transmitted ...
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An overview on the complete switching and conferencing IC-family is shown in the following table: Table 1 Complete Switching and Conferencing IC Family MTSC MTSS PEB 2045 PEB 2046 Switching 512 256 256 256 capacity (time-slots) Input/output ‘16/8 ‘8/8 lines ...
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Conferencing An important task in PCM voice handling is conferencing. I.e. several subscribers of a digital PBX system would like to arrange a conference call. This task will be done in the central switching network. Modern switching IC like the ...
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Figure 2 Data Flow through the MUSAC-A in Case of Conferencing Semiconductor Group 9 PEB 2445 Overview 02.96 ...
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The PCM samples of each input channel first pass through an input processing stage. In this stage, an input attenuation level ( dB) and a noise suppression threshold can be programmed individually for each channel. Following ...
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Multipoint Switching and Conferencing Unit - Attenuation TM MUSAC -A Version 1.2 1.1 Features Switching • Time/space switch for 2048-, 4096- or 8192-kbit/s PCM systems • Switching 512 incoming PCM channels 256 outgoing PCM ...
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Conference Mode • conference channels in any combination • independent conferences simultaneously (3 subscribers) • Programmable attenuation (0/3/6/9 dB) on each input channel • Programmable attenuation (0/3 dB) on each output channel • Programmable ...
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Pin Configuration (top view) Semiconductor Group P-LCC-44 13 PEB 2445 Overview 02.96 ...
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Pin Definitions and Functions Pin No. Symbol Input (I) P-LCC Output ( INT OD open drain IN1 I 7 IN5 I 9 IN9 I 11 IN13 I 13 IN14 I ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-LCC Output ( ALE I 26 AD0 I/O 27 AD1 I/O 29 AD2 I/O 30 ...
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Pin Definitions and Functions (cont’d) Pin No. Symbol Input (I) P-LCC Output (O) 35 OUT7 O 36 OUT6 O 37 OUT5 O 38 OUT4 O 40 OUT3 O 41 OUT2 O 42 OUT1 O 43 OUT0 O 39 RES ...
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Functional Symbols Figure 4 Functional Symbol for the Standard Configuration Figure 5 Functional Symbol for the Primary Access Configuration Semiconductor Group 17 PEB 2445 Overview 02.96 ...
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Device Overview The Multipoint Switching and Conferencing Unit (MUSAC-A) combines a time switch unit (MTSC) and a powerful signal processor on one chip. The MUSAC-A enhances the capabilities of a PBX by supporting teleconferencing and multipoint data communication over ...
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System Integration Conferencing The MUSAC-A is designed to connect any of the 512 PCM-input channels to any of 256 output channels. Any input channel total number of 64 can be handled in 21 independent conferences simultaneously. ...
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Figure 8 shows the architecture of a primary access board with common channel signaling using four CMOS devices. Figure 8 Architecture of a Primary Access Board Semiconductor Group 20 PEB 2445 Overview 02.96 ...
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Multipoint Switching In a multipoint configuration the communication between different stations is done by using a common media PBX system this can be achieved by connecting all stations to one (or more) time-slots and transmitting the information back. ...
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In order to establish a multipoint-connection with more than 64 terminals, you can form a multistage arrangement, as shown in figure 10. Figure 10 Multistage Arrangement Semiconductor Group 22 PEB 2445 Overview 02.96 ...
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Functional Description Figure 11 Detailed Block Diagram of the PEB 2445 Semiconductor Group Functional Description 23 PEB 2445 02.96 ...
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Basic Functional Principles The MUSAC memory time switch device for a PCM PBX system, offering a variety of additional features like multipoint switching, conference calls, programmable noise suppression and attenuation. The MUSAC-A works either in standard configuration ...
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CCM include the input time-slot and line number, the associated conference number as well as the noise suppression thresholds and the attenuation levels. The conference number defines a unique location in the Conference Sum Memory (CSM) used ...
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Definitions • The PEB 2445 works with either an 8192-kHz clock or a 4096-kHz clock. Henceforth, the respective clock periods are referred to as • The bits of a time-slot are numbered 0 through 7. Bit 0 (MSB ...
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As can be seen there the beginning of a input time-slot is defined such, that the input lines have settled to a stable value, when the datum is actually sampled. 4096- and 8192-kbit/s data is sampled in the middle of ...
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Figure 12 Latching Instant for Input Data Semiconductor Group Functional Description 28 PEB 2445 02.96 ...
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The four most significant bits of the clock shift register are of interest for the input lines. They only affect the odd input lines (see chapter 4.6.2): The frame structure can be advanced by the number of bit periods programmed ...
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Figure 13 shows when the single bits are output. In standard configuration they are clocked off at the rising clock edge at the beginning of the considered bit period. t Time-slot 0 starts two CP8 In primary access configuration the ...
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Time Slot 127 - 6 7 Time Slot Time Slot Time Slot 127 - 6 7 Time Slot Time Slot 31 6 Time ...
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Configuration Type The MUSAC-A works either in the standard configuration for usual switching applications or in the primary access configuration. In these both configurations the conference and multipoint switching capability can be used. Standard Configuration A logical 1 in the ...
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user defined integer. By varying N, steps. For an example using refer to figure 14. Figure 14 SP Duration for Primary Access Configuration A logical 0 in the CFS bit of ...
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In the primary access configuration only those modes which support at least 4 input and 4 output lines at 2048 kbit/s can be used. These are the modes Ml1, Ml0, MO1, MO0 = (see table ...
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Microprocessor Interface and Registers The MUSAC-A is programmed via the P interface. It consists of the address data bus AD7 AD0, the address bits A1 Latch Enable (ALE), the Interrupt (INT) and the Chip Select (CS) signal, as shown ...
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Five directly addressable registers are provided: • Mode register (MOD) • Status register (STA) • Conference Status register (CST) • Conference Mask Register (CMR) • Indirect Access Register (IAR) Two other registers and the control memories are accessed by a ...
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Indirect access to the CFR, CSR CCM: An indirect access is performed by reading/writing three consecutive bytes (first byte = control byte, second byte = data byte, third byte = address byte) to/from IAR. Bit ...
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Figure 17 Timing Diagrams of IAR Semiconductor Group Functional Description 38 PEB 2445 02.96 ...
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Operational Description 3.1 Reset State After a hardware reset (RES) or power up the MUSAC-A is set to its initial state. The MOD- and CFR register bits are all set to logical 1; the CSR-, CST- and CMR-register bits ...
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Figure 19 Initializing the PEB 2445 for a 4096-kHz Device Clock 3.3 Operation with a 4096-kHz Device Clock In order for the MUSAC-A to operate with a 4096-kHz device clock the CPS bit in the CFR register needs to be ...
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Detailed Register Description The following registers may be accessed: Table 6 Addressing the Direct Registers Address Demultiplexed Mode Multiplexed Mode A(1:0) AD(7: not connected ...
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Table 7 Input/Output Operating Modes MI1 MI0 MO1 ...
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Input Pin Arrangement Table 8 Input and Output Pin Arrangement for the Standard Configuration Pin No Mbit Mbit/s 4 IN1 5 IN0 7 IN5 8 IN4 9 IN9 10 IN8 11 IN13 12 IN12 13 IN14 ...
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Table 9 Input, Output and Tristate Pin Arrangement for the Primary Access Configuration Pin No. Pin Name P-LCC TSC0 5 TSC1 8 TSC2 10 TSC3 12 OUT0 43 OUT2 41 OUT4 38 OUT6 36 IN13 11 IN9 9 IN5 7 ...
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Status Register (STA) Access in the multiplexed P-interface mode: Access in the demultiplexed P-interface mode: AD7 don’t care B Busy: The chip is busy resetting the connection memory ( undefined after power ...
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Conference Mask Register (CMR) Access in the multiplexed P-interface mode: Access in the demultiplexed P-interface mode: Reset value AD7 logical 1 disables the corresponding interrupt. IR Initialization Request mask; the initialization request is masked ...
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Attenuation Table 10 Transparent Switching C3 C0 Attenuation ...
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Access to CM Transparent Switching (i.e. the MUSAC-A works exactly like a MTSC Validity bit: A logical 0 enables the programmed connection, a logical 1 tristates the outputs D8 D0 Logical line and time-slot number ...
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Standard Configuration Table 12 Time-Slot and Line Programming for Standard Configuration Standard configuration, all modes except space switch mode 2-Mbit/s input lines 4-Mbit/s input lines 8-Mbit/s input lines 2-Mbit/s output lines 4-Mbit/s output lines 8-Mbit/s output lines Semiconductor Group Bit ...
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Primary Access Configuration Table 13 Time-Slot and Line Programming for the Primary Access Configuration 2-Mbit/s input lines 4-Mbit/s input lines 8-Mbit/s input lines 2-Mbit/s output lines 4-Mbit/s output lines 8-Mbit/s output lines Semiconductor Group Bit Bit D3 ...
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The interface select bits have to be programmed as shown in the following table: Table 14 Interface Selection Bits System Interface Input lines 01 Output lines 0 Access 1 to CCM C3 C0 Logical Inversion ...
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Table Table Table 17 D5 Output Attenuation Level Note: The sequence of ...
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Indirect Registers 4.6.1 Configuration Register (CFR) Access: Read or write at address FE Reset value AD7 1 1 CPS Clock Period Select: Device clock is set to 8192 kHz (logical 1) or 4096 kHz (logical 0). CFS ...
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Clock Shift Register (CSR) Access: Read or write at address FF Reset value AD7 RS2 RS1 RS2 RS0 Receive clock Shift, bits 2 – 0. The received data stream is shifted in bit period steps. RRE Receive ...
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Figure 20 Clock Shifting Semiconductor Group Detailed Register Description 55 PEB 2445 02.96 ...
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Electrical Characteristics Absolute Maximum Ratings Parameter Ambient temperature under bias: PEB Storage temperature Voltage on any pin with respect to ground Maximum voltage on any pin Note: Stresses above those listed here may cause permanent damage to the device. ...
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Capacitances Parameter Input capacitance Output capacitance I/O 5.3 AC-Characteristics Ambient temperature under bias range, Inputs are driven to 2.4 V for a logical ‘1’ and to 0.4 ...
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Figure 23 P Write Cycle Figure 24 Multiplexed Address Timing Figure 25 Non-multiplexed Address Timing Semiconductor Group Electrical Characteristics 58 PEB 2445 02.96 ...
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Table 18 Microprocessor Interface Timing Parameter ALE pulse width Address setup time to ALE Address hold time from ALE Address latch setup time to WR, RD Address setup time to WR, RD Address hold time from WR, RD ALE pulse ...
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Clock and Synchronization Timing Table 20 PCM Interface Timing Parameter Clock period 8 MHz high Clock period 8 MHz low Clock period 8 MHz Synchronization pulse setup 8 MHz Synchronization pulse delay 8 MHz Clock period 4 MHz high ...
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Figure 26 PCM Line Timing in Standard Configuration with a 8 MHz Device Clock Semiconductor Group Electrical Characteristics 61 PEB 2445 02.96 ...
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Figure 27 PCM Line Timing in Primary Access Configuration with a 8 MHz Device Clock and a CSR Entry (00010001) Semiconductor Group Electrical Characteristics 62 PEB 2445 02.96 ...
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Figure 28 PCM Line Timing in Standard Configuration with a 4 MHz Device Clock Semiconductor Group Electrical Characteristics 63 PEB 2445 02.96 ...
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Figure 29 PCM Line Timing in Primary Access Configuration with a 4 MHz Device Clock and a CSR Entry (00010001) Semiconductor Group Electrical Characteristics 64 PEB 2445 02.96 ...
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Package Outlines P-LCC-44 (SMD) (Plastic Leaded Chip Carrier) Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book “Package Information” Surface Mounted Device Semiconductor Group 65 PEB 2445 Package Outlines Dimensions in ...
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Appendix 7.1 Initialization for Conferencing in a PBX 1) See table 7 2) See table 8 Semiconductor Group 66 PEB 2445 Appendix 02.96 ...
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Programming a Conference in a PBX Figure 30 Table 21 Procedure for each Conference 1. Make a list of the conference subscribers 2. Determine the input time slot Determine the logical input port 3. Determine the output time slot ...
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Programming Procedure for Switching TS’s – Select a column for input and output rate – Fill in the values of the bits – Write the 3 bytes (from top to bottom) to register IAR 2 MBit/s Output Rate 3 ...
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Programming Procedure for a PBX Conference – Select a column for input and output rate – Fill in the values of the bits by aid of chapter 7.1 and 7.2 – Write the 9 bytes (from top to bottom) ...
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INV PCM data inverted (= 1) or not (= 0) ITS6 0 Input time slot number IL0 3 Logical input line number CCA5 0 Conference control address NOI1 0 Noise suppression threshold noise suppression ...