PRIXP425ABD

Manufacturer Part NumberPRIXP425ABD
ManufacturerIntel
PRIXP425ABD datasheet
 

Specifications of PRIXP425ABD

Core Operating Frequency533MHzPackage TypeBGA
Pin Count492MountingSurface Mount
Operating Temperature (max)70COperating Temperature (min)0C
Operating Temperature ClassificationCommercialLead Free Status / Rohs StatusCompliant
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
9
Page 9
10
Page 10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Page 1/128

Download datasheet (3Mb)Embed
Next
®
Intel
IXP42X Product Line of Network
Processors and IXC1100 Control Plane
Processor
Product Features
For a complete list of product features, see
The following features do
not require enabling
software:
Intel XScale
MHz
PCI Interface
USB v1.1 Device Controller
SDRAM Interface
High-Speed UART
Console UART
Internal Bus Performance Monitoring
Unit
16 GPIOs
Four Internal Timers
Packaging
— 492-pin PBGA
Commercial/Extended Temperature
Typical Applications
High-Performance DSL Modem
High-Performance Cable Modem
Residential Gateway
SME Router
Network Printers
“Product Features” on page
The following features do
require enabling software:
®
Processor — Up to 533
Note:
Datasheet
10.
Encryption/Authentication
(AES,DES,3DES,SHA-1,MD5)
Two High-Speed, Serial Interfaces
Three Network Processor Engines
Up to two MII Interfaces
One UTOPIA Level 2 Interface
Multi-Channel HDLC
®
Refer to the Intel
IXP400 Software
Programmer’s Guide for information on
which features are currently enabled.
Control Plane
Integrated Access Device (IAD)
Set-Top Box
Access Points (802.11a/b/g)
Industrial Controllers
Document Number: 252479-007US
June 2007

PRIXP425ABD Summary of contents

  • Page 1

    ... Two High-Speed, Serial Interfaces Three Network Processor Engines Up to two MII Interfaces One UTOPIA Level 2 Interface Multi-Channel HDLC ® Refer to the Intel IXP400 Software Programmer’s Guide for information on which features are currently enabled. Control Plane Integrated Access Device (IAD) Set-Top Box Access Points (802 ...

  • Page 2

    ... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...

  • Page 3

    ... High-Speed and Console UARTs ............................................................... 23 2.1.11 GPIO .................................................................................................... 23 2.1.12 Internal Bus Performance Monitoring Unit (IBPMU) ..................................... 23 2.1.13 Interrupt Controller ................................................................................ 24 2.1.14 Timers .................................................................................................. 24 2.1.15 AHB Queue Manager............................................................................... 24 ® 2.2 Intel XScale Processor ..................................................................................... 24 2.2.1 Super Pipeline........................................................................................ 25 2.2.2 Branch Target Buffer (BTB)...................................................................... 26 2.2.3 Instruction Memory Management Unit (IMMU)............................................ 27 2 ...

  • Page 4

    ... Power Sequence .............................................................................................. 125 5.7 I and Total Average Power ............................................................................. 126 CC 6.0 Ordering Information............................................................................................. 128 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 4 ® Intel IXP42X product line and IXC1100 control plane processors Document Number: 252479-007US June 2007 ...

  • Page 5

    ... Intel IXP422 Network Processor Block Diagram .......................................................... 17 ® 4 Intel IXP421 Network Processor Block Diagram .......................................................... 17 ® 5 Intel IXP420 Network Processor Block Diagram .......................................................... 18 ® 6 Intel XScale Technology Block Diagram..................................................................... 25 7 492-Pin Lead PBGA Package ...................................................................................... 47 8 Package Markings .................................................................................................... Power Filtering Diagram................................................................................. 78 CCPLL1 10 V Power Filtering Diagram................................................................................. 79 ...

  • Page 6

    ... Part Numbers for the Intel 22 Ball Map Assignment for the Intel 23 Ball Map Assignment for the Intel 24 Ball Map Assignment for the Intel 25 Ball Map Assignment for the Intel Plane Processor ........................................................................................................70 26 Operating Conditions ................................................................................................81 27 PCI DC Parameters ...................................................................................................81 28 USB v1.1 DC Parameters ...........................................................................................81 29 UTOPIA Level 2 DC Parameters ...

  • Page 7

    ... SDRAM Output Timings Values................................................................................... 94 55 Signal Timing With Respect to Clock Rising Edge .......................................................... 95 ® 56 Intel Multiplexed Mode Values.................................................................................. 98 57 Intel Simplex Mode Values ...................................................................................... 101 58 Motorola* Multiplexed Mode Values .......................................................................... 103 59 Motorola* Simplex Mode Values ............................................................................... 105 60 HPI Timing Symbol Description ................................................................................ 109 61 HPI-8 Mode Write Access Values .............................................................................. 109 62 HPI-16 Multiplexed Write Accesses Values ...

  • Page 8

    ... Corrected the maximum Talepulse value in 9. Clarified ordering information in ® 10. Updated Intel product branding. References to Intel XScale core were updated to Intel XScale Processor 11. Incorporated specification changes, specification clarifications and document ® changes from the Intel IXP4XX Product Line of Network Processors Specification Update (306428-004) 1 ...

  • Page 9

    ... Detailed functional descriptions other than parametric performance are published in the Intel Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual. ...

  • Page 10

    ... This section outlines the features that apply to the Intel Network Processors and IXC1100 Control Plane Processor. Some of the features described in this document require enablement by software delivered by Intel. Some features may not be enabled with current software releases. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ...

  • Page 11

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors The features that require software are identified below. Refer to the Intel Software Programmer’s Guide for information on features that are currently enabled ® • Intel XScale — High-performance processor based on Intel XScale — ...

  • Page 12

    ... Support for 8 MB, minimum 256 MB maximum • Expansion interface — 24-bit address — 16-bit data — Eight programmable chip selects — Supports Intel/Motorola* microprocessors • Multiplexed-style bus cycles • Simplex-style bus cycles • DSP support for: — Texas Instruments* DSPs supporting HPI-8 bus cycles • ...

  • Page 13

    ... Supports speeds up to 8.192 MHz — Supports connection to T1/E1 framers — Supports connection to CODEC/SLICs — Eight HDLC Channels Note: This feature requires Intel supplied software. To determine if this feature is enabled by a particular software release, see the Intel 1.2.2 Processor Features Table 3 on page 13 of Network Processors and IXC1100 Control Plane Processor ...

  • Page 14

    ... Commercial X Temperature Extended X Temperature Notes: 1. The features marked “Yes” require enabling software. Refer to the Intel determine if the feature is enabled. 2. Only the 266 MHz version of the Intel 2.0 Functional Overview ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor are compliant with the ARM ® ...

  • Page 15

    ... North AHB SHA-1/MD5, Arbiter DES/3DES, AES North/South South AHB AHB Bridge AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale Processor fi (AHB) 266/400/533 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache Unit 2 KB Mini-Data Cache ® ...

  • Page 16

    ... North AHB Ethernet MAC Arbiter North/South South AHB AHB Bridge Arbiter AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale Processor fi (AHB) 266/533 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache Unit 2 KB Mini-Data Cache Queue ...

  • Page 17

    ... North AHB Ethernet MAC Arbiter North/South South AHB AHB Bridge Arbiter AHB/APB 133.32 MHz x 32 bits South Advance High-Performance Bus Bridge PMU Intel XScale Intel XScale Processor Core fi fi (AHB) 266 MHz 32 KB Data Cache Test Logic 32 KB Instruction Cache ...

  • Page 18

    ... Functional Units The following sections briefly the functional units and their interaction in the system. For more detailed information, refer to the Intel Processors and IXC1100 Control Plane Processor Developer’s Manual. Unless otherwise specified, the functional descriptions apply to all processors in the IXP42X product line and IXC1100 control plane processors ...

  • Page 19

    ... These coprocessors are implemented in hardware, enabling the coprocessors and the NPE processor core to operate in parallel. The combined forces of the hardware multi-threading, local-code store, independent instruction memory, independent data memory, and parallel processing allows the Intel ® XScale processor to be utilized for application purposes. The multi-processing ...

  • Page 20

    ... South AHB The South AHB is a 133.32 MHz, 32-bit bus that can be mastered by the Intel XScale processor, PCI controller, and the AHB/AHB bridge. The targets of the South AHB Bus can be the SDRAM, PCI interface, queue manager, expansion bus, or the APB/AHB bridge ...

  • Page 21

    ... PCI Local Bus Specification, Rev. 2.2. The PCI interface is 32-bit compatible bus and capable of operating as either a host or an option (that is, not the Host) For more information on PCI Controller support and configuration see the Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’ ...

  • Page 22

    ... External pull-up/ pull-down resistors are used to tie the signals to particular logic levels. For additional details, refer to Section 8 (Expansion Bus Controller) of the Intel of Network Processors and IXC1100 Control Plane Processor Developer’s Manual.) ® ...

  • Page 23

    ... Interrupt Controller The IXP42X product line and IXC1100 control plane processors consists of 32 interrupt sources to allow an extension of the Intel XScale sources. These sources can originate from some external GPIO pins or internal peripheral interfaces. The interrupt controller can configure each interrupt source as an FIQ, IRQ, or disabled. ...

  • Page 24

    ... The AQM interfaces include an Advanced High-performance Bus (AHB) interface to the NPEs and Intel XScale an event bus (to the NPE condition select logic) and two interrupts to the Intel XScale processor. The AHB interface is used for configuration of the AQM and provides access to queues, queue status and SRAM. Individual queue status for queues 0-31 is communicated to the NPEs via the flag bus ...

  • Page 25

    ... Performance monitoring unit (PMU) furnishing two 32-bit event counters and one 32-bit cycle counter for analysis of hit rates, etc. This PMU is for the Intel XScale monitoring of internal bus performance. • JTAG debug unit that uses hardware break points and 256-entry trace history buffer (for flow-change messages) to debug programs ® ...

  • Page 26

    ... ITLB entries zero through 30 can be locked. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 26 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet • Weakly taken • Weakly not taken • Strongly not taken June 2007 ...

  • Page 27

    ... ITLB. Access permissions for each memory domains can be programmed. When an instruction pre-fetch is attempted to an area of memory in violation of access permissions, the attempt is aborted and a pre-fetch abort is sent to the Intel XScale processor for exception processing. The IMMU and DMMU can be enabled or disabled together. ...

  • Page 28

    ... Fill Buffer (FB) and Pend Buffer (PB) The four-entry fill buffer (FB) works with the Intel XScale non-cacheable loads until the bus controller can act on them. The FB and the four-entry pend buffer (PB) work with the D-cache and mini-data cache to provide “hit-under-miss” capability, allowing the Intel XScale the caches while “ ...

  • Page 29

    ... The signed multiply-accumulates (MIA) multiply a 32-bit, Intel XScale processor general register (multiplier) and another 32-bit, Intel XScale general register (multiplicand) to produce a 64-bit product where the 40 LSBs are added to the 40-bit accumulator ...

  • Page 30

    ... Debug exceptions are instruction breakpoint, data breakpoint, software breakpoint, external debug breakpoint, exception vector trap, and trace buffer full breakpoint. Once execution has stopped, the debugger application code can examine or modify the Intel ® XScale processor’s state, coprocessor state, or memory. The debugger application code can then restart program execution. The debug unit has two hardware-instruction, break point registers ...

  • Page 31

    ... A signal called active low specifies that the interface is active when driven to a logic 0 and inactive when driven to a logic 1. June 2007 Document Number: 252479-007US Description Reference ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 31 ...

  • Page 32

    ... The Post Reset column indicates signal state for the following condition: — Post Reset is defined as follows: PWRON_RESET_N = 1, RESET_IN_N = 1 and PLL_LOCK = 1 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 32 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet June 2007 Document Number: 252479-007US ...

  • Page 33

    ... SDRAM Clock Enable: CKE is driving high to activate the clock to an external SDRAM and driven low to de- O activate the CLK to an external SDRAM. O SDRAM Data bus mask: DQM is used to byte select data during read/write access to an external SDRAM. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 34

    ... PCI arbitration request: Used by the internal PCI arbiter to allow an agent to request the PCI bus. I Should be pulled high with a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 35

    ... CLK and timing parameters are defined with respect to this edge. The PCI I clock rate can operate MHz. †† Should be pulled high with a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 36

    ... KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset. I/O †† Should be pulled high with a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 37

    ... KHz to 8.192 MHz. Used to sample the received data. Configured as an input upon reset. I/O †† Should be pulled high with a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 38

    ... Management data clock. Management data interface clock is used to clock the MDIO signal as an output and IO sample the MDIO as an input. The ETH_MDC is an input on power up and can be configured output ® through an Intel API as documented in the Intel IXP400 Software Programmer’s Guide. Table 5 on page 30. ...

  • Page 39

    ... CRS asynchronously and de-asserts synchronously with respect to ETH_RXCLK1. †† Should be pulled high through a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 40

    ... In SPHY mode, this signal is used to indicate to the processor that the PHY has an octet or cell available to be transferred to the processor. †† Should be pulled high through a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 41

    ... Description I Input clock signal used to sample all expansion interface inputs and clock all expansion interface outputs. Address-latch enable used for multiplexed address/data bus accesses. Used in Intel and Motorola* multiplexed O modes of operation. Expansion-bus address used as an output for data accesses over the expansion bus. Also, used as an input during reset to capture device configuration ...

  • Page 42

    ... Data ready/acknowledge from expansion-bus devices. Expansion-bus access is halted when an external device sets EX_IOWAIT_N to logic 0 and resume from the halted location once the external device sets EX_IOWAIT_N to logic 1. This signal affects accesses that use EX_CS_N[7:0] when the chip select is configured in Intel Motorola-mode of operation. ...

  • Page 43

    ... LOOP-mode operation holds this signal in its inactive state (logic 1). Console UART Pins. Table 5 on page 30. † Description I/O Positive signal of the differential USB receiver/driver. I/O Negative signal of the differential USB receiver/driver. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 44

    ... MHz with various duty cycles. Configured as an output, upon reset. Can be used to clock the expansion interface, after reset. †† Should be pulled high though a 10-KΩ resistor when not being utilized in the system. Table 5 on page 30. ® Intel IXP45X and Intel ® IXP46X Product Line of Network Processors Datasheet Document Number: 252479-007US ...

  • Page 45

    ... For a legend of the Type codes, see †† IMPORTANT NOTE: When a system-level reset is asserted to the Intel Processor — either via a power-on reset, a system reset Watchdog-Timer reset — and any interface active transaction (particularly the PCI bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a reset of other attached devices may be required ...

  • Page 46

    ... For a legend of the Type codes, see †† IMPORTANT NOTE: When a system-level reset is asserted to the Intel Processor — either via a power-on reset, a system reset Watchdog-Timer reset — and any interface active transaction (particularly the PCI bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior of the IXP42X product line and IXC1100 control plane processors is undefined in this situation and a reset of other attached devices may be required ...

  • Page 47

    ... IXP42X product line and IXC1100 control plane processors 4.0 Package and Pinout Information ® The Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, plastic ball grid array (PBGA) package for commercial-temperature applications and a pin-for-pin, compatible 492-ball, plastic ball grid array with a drop-in heat spreader (H) for extended-temperature applications ...

  • Page 48

    ... B-1 266 B-1 266 Yes * Level 1 Name BSMC (ATPO#, Date Code and COO) Lead Part # Free Yes EWIXP425ABDT Yes EWIXP425ABBT Yes PRIXP425ABD Yes PRIXP425ABC Yes PRIXP425ABB GWIXP425ABDT GWIXP425ABCT GWIXP425ABBT FWIXP425ABD FWIXP425ABC FWIXP425ABB Yes PRIXP423ABD FWIXP423ABD Yes PRIXP423ABB FWIXP423ABB Yes PRIXP422ABB ...

  • Page 49

    ... Intel IXP425 Network Processor ® Intel IXP423 Network Processor ® Intel IXP422 Network Processor ® Intel IXP421 Network Processor ® Intel IXP420 Network Processor and Intel Table 22. Ball Map Assignment for the Intel Ball Signal Ball A1 PCI_AD[27 PCI_GNT_N[ PCI_GNT_N[ SDM_DATA[19] B4 ...

  • Page 50

    ... Table 22. Ball Map Assignment for the Intel Ball Signal Ball A22 SDM_ADDR[5] B22 A23 EX_RD_N B23 A24 EX_ADDR[1] B24 A25 EX_ADDR[3] B25 A26 EX_ADDR[5] B26 E1 PCI_AD[23 VCCP F2 E3 PCI_REQ_N[ VSS F4 E5 PCI_GNT_N[ SDM_DATA[16 VCCP F7 E8 SDM_DATA[30 VSS F9 E10 SDM_DATA[22] F10 E11 ...

  • Page 51

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal Ball J1 PCI_CLKIN K1 J2 VCCP K2 J3 VSS K3 J4 PCI_AD[22 VSS K5 J6 PCI_AD[29] K6 J21 EX_ADDR[8] K21 J22 EX_ADDR[16] K22 J23 VCC K23 J24 ...

  • Page 52

    ... Table 22. Ball Map Assignment for the Intel Ball Signal Ball N1 PCI_AD[11 VCCP P2 N3 VCC P3 N4 PCI_PERR_N P4 N5 PCI_AD[15] P5 N11 VSS P11 N12 VSS P12 N13 VSS P13 N14 VSS P14 N15 VSS P15 N16 VSS P16 N22 VCC P22 N23 VSS ...

  • Page 53

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal Ball U1 PCI_AD[ VCCP V2 U3 PCI_AD[ PCI_AD[ HSS_TXDATA0 V5 U6 VCC V6 U21 VCC V21 U22 GPIO[14] V22 U23 EX_RDY_N[1] V23 U24 EX_RDY_N[2] V24 ...

  • Page 54

    ... Table 22. Ball Map Assignment for the Intel Ball Signal Ball AA1 HSS_RXDATA0 AB1 AA2 VCCP AB2 AA3 VSS AB3 AA4 HSS_RXCLK1 AB4 AA5 ETH_TXDATA0[2] AB5 AA6 VCC AB6 AA7 ETH_RXDATA0[1] AB7 AA8 VSS AB8 AA9 ETH_TXDATA1[1] AB9 AA10 VCC AB10 AB11 ...

  • Page 55

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 22. Ball Map Assignment for the Intel Ball Signal Ball AE1 ETH_RXDATA0[3] AF1 AE2 VCCP AF2 AE3 ETH_COL0 AF3 AE4 ETH_TXEN1 AF4 AE5 VCCP AF5 AE6 ETH_RXDV1 AF6 AE7 VSS ...

  • Page 56

    ... Table 23. Ball Map Assignment for the Intel Ball Signal Ball A1 PCI_AD[27 PCI_GNT_N[ PCI_GNT_N[ SDM_DATA[19 SDM_DATA[27 SDM_DATA[26 SDM_DATA[25 SDM_DATA[23 SDM_DATA[14] B9 A10 SDM_DATA[13] B10 A11 SDM_DATA[11] B11 A12 SDM_DATA[10] B12 A13 SDM_DATA[6] B13 A14 SDM_DATA[8] B14 A15 SDM_DQM[1] B15 A16 SDM_CS_N[0] B16 A17 ...

  • Page 57

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal Ball E1 PCI_AD[23 VCCP F2 E3 PCI_REQ_N[ VSS F4 E5 PCI_GNT_N[ SDM_DATA[16 VCCP F7 E8 SDM_DATA[30 VSS F9 E10 SDM_DATA[22] F10 E11 VCCP E12 SDM_DATA[3] E13 ...

  • Page 58

    ... Table 23. Ball Map Assignment for the Intel Ball Signal Ball J1 PCI_CLKIN K1 J2 VCCP K2 J3 VSS K3 J4 PCI_AD[22 VSS K5 J6 PCI_AD[29] K6 J21 EX_ADDR[8] K21 J22 EX_ADDR[16] K22 J23 VCC K23 J24 EX_ADDR[23] K24 J25 EX_CS_N[2] K25 J26 EX_CS_N[4] K26 Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 59

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal Ball N1 PCI_AD[11 VCCP P2 N3 VCC P3 N4 PCI_PERR_N P4 N5 PCI_AD[15] P5 N11 VSS P11 N12 VSS P12 N13 VSS P13 N14 VSS P14 ...

  • Page 60

    ... Table 23. Ball Map Assignment for the Intel Ball Signal Ball U1 PCI_AD[ VCCP V2 U3 PCI_AD[ PCI_AD[ N VCC V6 U21 VCC V21 U22 GPIO[14] V22 U23 EX_RDY_N[1] V23 U24 EX_RDY_N[2] V24 U25 GPIO[15] V25 U26 EX_DATA[15] V26 Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 61

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 23. Ball Map Assignment for the Intel Ball Signal Ball AA1 N/C AB1 AA2 VCCP AB2 AA3 VSS AB3 AA4 N/C AB4 AA5 ETH_TXDATA0[2] AB5 AA6 VCC AB6 AA7 ETH_RXDATA0[1] ...

  • Page 62

    ... Table 23. Ball Map Assignment for the Intel Ball Signal Ball AE1 ETH_RXDATA0[3] AF1 AE2 VCCP AF2 AE3 ETH_COL0 AF3 AE4 ETH_TXEN1 AF4 AE5 VCCP AF5 AE6 ETH_RXDV1 AF6 AE7 VSS AF7 AE8 ETH_COL1 AF8 AE9 VCCP AF9 AE10 VCCPLL1 AF10 AE11 ...

  • Page 63

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal Ball A1 PCI_AD[27 PCI_GNT_N[ PCI_GNT_N[ SDM_DATA[19 SDM_DATA[27 SDM_DATA[26 SDM_DATA[25 SDM_DATA[23 SDM_DATA[14] B9 A10 SDM_DATA[13] B10 A11 SDM_DATA[11] B11 A12 SDM_DATA[10] B12 A13 SDM_DATA[6] ...

  • Page 64

    ... Table 24. Ball Map Assignment for the Intel Ball Signal Ball E1 PCI_AD[23 VCCP F2 E3 PCI_REQ_N[ VSS F4 E5 PCI_GNT_N[ SDM_DATA[16 VCCP F7 E8 SDM_DATA[30 VSS F9 E10 SDM_DATA[22] F10 E11 VCCP E12 SDM_DATA[3] E13 VSS E14 SDM_DQM[0] E15 VCCP E16 SDM_BA[0] E17 VSS F17 E18 ...

  • Page 65

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal Ball J1 PCI_CLKIN K1 J2 VCCP K2 J3 VSS K3 J4 PCI_AD[22 VSS K5 J6 PCI_AD[29] K6 J21 EX_ADDR[8] K21 J22 EX_ADDR[16] K22 J23 VCC K23 J24 ...

  • Page 66

    ... Table 24. Ball Map Assignment for the Intel Ball Signal Ball N1 PCI_AD[11 VCCP P2 N3 VCC P3 N4 PCI_PERR_N P4 N5 PCI_AD[15] P5 N11 VSS P11 N12 VSS P12 N13 VSS P13 N14 VSS P14 N15 VSS P15 N16 VSS P16 N22 VCC P22 N23 VSS ...

  • Page 67

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal Ball U1 PCI_AD[ VCCP V2 U3 PCI_AD[ PCI_AD[ HSS_TXDATA0 V5 U6 VCC V6 U21 VCC V21 U22 GPIO[14] V22 U23 EX_RDY_N[1] V23 U24 EX_RDY_N[2] V24 ...

  • Page 68

    ... Table 24. Ball Map Assignment for the Intel Ball Signal Ball AA1 HSS_RXDATA0 AB1 AA2 VCCP AB2 AA3 VSS AB3 AA4 HSS_RXCLK1 AB4 AA5 ETH_TXDATA0[2] AB5 AA6 VCC AB6 AA7 ETH_RXDATA0[1] AB7 AA8 VSS AB8 AA9 N/C AB9 AA10 VCC AB10 AB11 ...

  • Page 69

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 24. Ball Map Assignment for the Intel Ball Signal Ball AE1 ETH_RXDATA0[3] AF1 AE2 VCCP AF2 AE3 ETH_COL0 AF3 AE4 N/C AF4 AE5 VCCP AF5 AE6 N/C AF6 AE7 VSS ...

  • Page 70

    ... Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball A1 PCI_AD[27 PCI_GNT_N[ PCI_GNT_N[ SDM_DATA[19 SDM_DATA[27 SDM_DATA[26 SDM_DATA[25 SDM_DATA[23 SDM_DATA[14] B9 A10 SDM_DATA[13] B10 A11 SDM_DATA[11] B11 A12 SDM_DATA[10] B12 A13 SDM_DATA[6] B13 A14 SDM_DATA[8] B14 A15 SDM_DQM[1] ...

  • Page 71

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball E1 PCI_AD[23 VCCP F2 E3 PCI_REQ_N[ VSS F4 E5 PCI_GNT_N[ SDM_DATA[16 VCCP F7 E8 SDM_DATA[30 VSS F9 E10 SDM_DATA[22] F10 ...

  • Page 72

    ... Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball J1 PCI_CLKIN K1 J2 VCCP K2 J3 VSS K3 J4 PCI_AD[22 VSS K5 J6 PCI_AD[29] K6 J21 EX_ADDR[8] K21 J22 EX_ADDR[16] K22 J23 VCC K23 J24 EX_ADDR[23] K24 J25 EX_CS_N[2] K25 J26 ...

  • Page 73

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball N1 PCI_AD[11 VCCP P2 N3 VCC P3 N4 PCI_PERR_N P4 N5 PCI_AD[15] P5 N11 VSS P11 N12 VSS P12 N13 ...

  • Page 74

    ... Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball U1 PCI_AD[ VCCP V2 U3 PCI_AD[ PCI_AD[ N VCC V6 U21 VCC V21 U22 GPIO[14] V22 U23 EX_RDY_N[1] V23 U24 EX_RDY_N[2] V24 U25 GPIO[15] V25 U26 EX_DATA[15] V26 Note: Interfaces not being utilized at a system level require external pull-up or pull-down resistors. For specific details and requirements, see Section 3.0, “ ...

  • Page 75

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball AA1 N/C AB1 AA2 VCCP AB2 AA3 VSS AB3 AA4 N/C AB4 AA5 ETH_TXDATA0[2] AB5 ...

  • Page 76

    ... Table 25. Ball Map Assignment for the Intel IXC1100 Control Plane Processor (Sheet Ball Signal Ball AE1 ETH_RXDATA0[3] AF1 AE2 VCCP AF2 AE3 ETH_COL0 AF3 AE4 ETH_TXEN1 AF4 AE5 VCCP AF5 AE6 ETH_RXDV1 AF6 AE7 VSS AF7 AE8 ETH_COL1 AF8 AE9 VCCP ...

  • Page 77

    ... Electrical Specifications 5.1 Absolute Maximum Ratings Parameter Ambient Air Temperature (Extended) Ambient Air Temperature (Commercial) Supply Voltage (Intel XScale Supply Voltage I/O Supply Voltage Oscillator (V Supply Voltage Oscillator (V Supply Voltage PLL (V Supply Voltage PLL (V Voltage On Any I/O Ball Storage Temperature Warning: Stressing the device beyond the “ ...

  • Page 78

    ... CCPLL1 CCPLL2 To reduce voltage-supply noise on the analog sections of the Intel Line of Network Processors and IXC1100 Control Plane Processor, the phase-lock loop circuits (V , CCPLL1 voltage supplies. The filter circuits for each supply are shown in the following sections. 5.2.1 V Requirement CCPLL1 A parallel combination of a 10-nF capacitor — for bypass — and a 200-nF capacitor — ...

  • Page 79

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane V SS Processor B1681-03 pin and V CCP_OSC SSP_OSC ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane Processor B1675-04 Datasheet 79 ...

  • Page 80

    ... V SS RCOMP ® Intel 34 Ω, ® Intel IXC1100 Control Plane + supply pin. Both SSOSC pin and the CCOSC ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane Processor B1676-03 IXP42X Product Line / Processor B1672-02 June 2007 Document Number: 252479-007US ...

  • Page 81

    ... OUT 0 < V < V -10 IN CCP Conditions I = OUT -6 IOUT = 6 < V < CCP ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Typ. Max. Units Notes 3.3 3.465 V 1.3 1.365 V 1.3 1.365 V 3.3 3.465 V 1.3 1.365 V 1.3 1.365 V Typ ...

  • Page 82

    ... Note: 1. These values are typical values seen by the manufacturing process and are not tested. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 82 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Conditions OUT OUT V > ...

  • Page 83

    ... IH (MAX) CCP = -2 V for a pulse width < cannot be exceeded. IL (MIN) Conditions Min. 2 2.4 OUT I = 4mA OUT 0 < V < V -10 IN CCP ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Typ. Max. Units Notes 10 µ Typ. Max. Units Notes V 1 0.8 ...

  • Page 84

    ... These values are typical values seen by the manufacturing process and are not tested. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 84 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Conditions Min. 2 2.4 OUT ...

  • Page 85

    ... Min. 2 2.4 OUT OUT 0 < V < V -10 IN CCP Conditions Min. 1.0 0 < V < IN -500 1.3V ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Typ. Max. Units 2.0 V 0.8 V 2.4 V 0.4 V 2.4 V 0.4 V -10 10 µA CCP 5 pF Typ ...

  • Page 86

    ... Refer to the application note titled Spread Spectrum Clocking to Reduce EMI Application Note, when designing a product that utilizes spread spectrum clocking. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 86 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Conditions Min. 2.0 (Oscillator Reference) Parameter Min. ...

  • Page 87

    ... IXP42X Product Line / ® Intel IXC1100 Control Plane Processor OSC_IN Oscillator OSC_OUT 33 MHz Parameter Min. Max Parameter Min. 35 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor B1678-03 66 MHz Units Notes Min. Max 1.5 4 V/ns Nom. Max. Units Notes ...

  • Page 88

    ... Figure 15. PCI Output Timing CLK Output Delay Note 0 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 88 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Parameter Min. 40 Parameter Min. 15. clk2out(b) and V = 0.2 V LOW CC Nom. ...

  • Page 89

    ... For additional information, see the PCI Local Bus Specification, Rev. 2.2. June 2007 Document Number: 252479-007US T setup(b) Inputs Valid 33 MHz Parameter Min. Max 10 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T hold A9573-01 66 MHz Units Notes Min. Max ...

  • Page 90

    ... UTP_IP_FCI, and UTP_OP_FCI. Figure 18. UTOPIA Level 2 Output Timings Clock Signals ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 90 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Tsetup Thold Parameter Tclk2out A9578-01 Min. Max. Units Notes ...

  • Page 91

    ... ETH_TXDATA and ETH_TXEN hold time after T 2 ETH_TXCLK. Note: 1. These values satisfy the MII specification requirement clock to output delay. June 2007 Document Number: 252479-007US Parameter T 1 Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Max. Units Notes A9580-01 Min ...

  • Page 92

    ... MDIO Figure 21. MDIO Output Timings ETH_MDC ETH_MDIO Note: NPE is sourcing MDIO. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 92 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Parameter A9581-01 Min. Max. Units Notes 5 ...

  • Page 93

    ... Input hold time after the rising edge of the clock. T Inputs included in this timing are SDM_DQ[31:0] hold (during a read operation). June 2007 Document Number: 252479-007US Parameter T setup Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T 4 A9583-02 Min. Max. Units Notes ETH_MDC ...

  • Page 94

    ... Note: 1. Timing test were performed with a 70-pF load to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 94 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Data Valid T clk2out Parameter T holdout A9584-01 Min. Max. ...

  • Page 95

    ... Control signal and data output valid after clock rising edge Input Setup time with respect to clock rising edge. Input Hold time with respect to clock rising edge. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles ...

  • Page 96

    ... EX_ADDR[23:0] EX_ALE EX_IOWAIT_N EX_RD_N EX_DATA[15:0] Valid Address ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 96 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T rdsetup Valid Data ...

  • Page 97

    ... June 2007 Document Number: 252479-007US 2-5 Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T wrpulse T dval2valwrt T ale2addrhold Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterwr B3748-001 Datasheet 97 ...

  • Page 98

    ... Timing tests were performed with a 70-pF capacitor to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 98 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Parameter Min. Max. Units Notes 1 4 Cycles ...

  • Page 99

    ... EX_ADDR[23:0] EX_IOWAIT_N EX_RD_N EX_DATA[15:0] June 2007 Document Number: 252479-007US 1-4 Cycles 1-4 Cycles 1-16 Cycles Valid Address T rdsetup Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T rdhold B3749-002 Datasheet 99 ...

  • Page 100

    ... EX_CLK EX_CS_N[0] EX_ADDR[23:0] EX_IOWAIT_N EX_WR_N EX_DATA[15:0] ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 100 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet 1-4 Cycles 1-4 Cycles 1-16 Cycles Valid Address T wrpulse T dval2valwrt ...

  • Page 101

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Table 57. Intel Simplex Mode Values Symbol Parameter T Valid address to valid chip select addr2valcs T Write data valid prior to EX_WR_N falling edge dval2valwrt T Pulse width of the EX_WR_N wrpulse T Valid data after the rising edge of EX_WR_N ...

  • Page 102

    ... EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] Valid Address ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 102 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet 2-5 Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T ...

  • Page 103

    ... Cycles 1-4 Cycles 1-16 Cycles T ale2valcs Valid Address T dspulse T dval2valds T ale2addrhold Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov B3752-001 Min. Max. Units Notes 1 4 Cycles ...

  • Page 104

    ... EX_IOWAIT_N EX_RD_N (exp_mot_rnw) EX_WR_N (exp_mot_ds_n) EX_DATA[15:0] ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 104 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet 1-4 Cycles 1-4 Cycles 1-16 Cycles T ad2valcs Valid Address T rdsetup Valid Data Min ...

  • Page 105

    ... 1-4 Cycles 1-4 Cycles 1-16 Cycles T ad2valcs Valid Address T dspulse T dval2valds Valid Data Parameter ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 T5 1-4 Cycles 1-16 Cycles T recov T dhold2afterds B3754-001 Min. Max. Units Notes 1 4 Cycles ...

  • Page 106

    ... Timing tests were performed with a 70-pF capacitor to ground. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 106 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Parameter Min. Max. Units Notes 15 ns ...

  • Page 107

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Figure 34. HPI-8 Mode Read Accesses June 2007 Document Number: 252479-007US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 107 ...

  • Page 108

    ... Figure 35. HPI-8 Mode Write Accesses ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 108 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet June 2007 Document Number: 252479-007US ...

  • Page 109

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 110

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 111

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Figure 36. HPI-16 Multiplexed Write Mode June 2007 Document Number: 252479-007US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 111 ...

  • Page 112

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 113

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Figure 37. HPI-16 Multiplex Read Mode June 2007 Document Number: 252479-007US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 113 ...

  • Page 114

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 115

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Figure 38. HPI-16 Simplex Read Mode June 2007 Document Number: 252479-007US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 115 ...

  • Page 116

    ... The data strobe phase parameter (T3) must be set to a minimum value of 1. This value allows two T clocks for the data phase. This setting is required to ensure that in the event of an HRDY, the Intel IXP42X Product Line and Intel recognize the HRDY and hold the data setup phase for at least one clock pulse after the HRDY is de- active ...

  • Page 117

    ... Datasheet—Intel IXP42X product line and IXC1100 control plane processors Figure 39. HPI-16 Simplex Write Mode June 2007 Document Number: 252479-007US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 117 ...

  • Page 118

    ... EX_DATA[15:0] Note: Notice that the access is an Intel-style simplex read access. The data strobe phase is set to a value to last three clock cycles. The data is returned from the peripheral device prior to the three clocks and the peripheral device de-asserts EX_IOWAIT_N. The data strobe phase terminates after two clocks even though the strobe phase was configured to pulse for three clocks. ® ...

  • Page 119

    ... EX_CS_ N[0] EX_ADDR[ EX_ IOWAIT_N EX_RD_N EX_DATA[15:0] June 2007 Document Number: 252479-007US T1=3 h T2 Cycles 4 Cycles 16 Cycles .... 2 Cycles Valid Address Valid Data ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor T4 Cycles 16 Cycles ... . B5243- 01 Datasheet 119 ...

  • Page 120

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 120 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet Valid Data Valid Data Valid Data ...

  • Page 121

    ... Timing tests were performed with a 70-pF capacitor to ground and a 10-KΩ pull-up resistor. For more information on the HSS Jitter Specifications see the Intel Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual. 5.5.2.9 JTAG Figure 43 ...

  • Page 122

    ... To successfully come out of reset, two things must occur: • Proper power sequence as described in ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 122 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet JTG_TRST_N T bsr JTG_TMS T T bsrs ...

  • Page 123

    ... A Soft Reset condition is accomplished by the usage of the hardware Watch-Dog Timer module, and software to manage and perform counter updates. For a complete description of Watch-Dog Timer functionality, refer to Watchdog Timer sub-section in the Timers Chapter of the Intel IXC1100 Control Plane Processor Developer’s Manual. The Soft Reset is similar to what is described in that there is no hardware requirement ...

  • Page 124

    ... Reset Timings Figure 45. Reset Timings ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet 124 ® Intel IXP42X product line and IXC1100 control plane processors—Datasheet June 2007 Document Number: 252479-007US ...

  • Page 125

    ... V ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Min. Typ. Max. Units Note 2000 µ 500 ns ® before the Intel XScale µs power-up pattern. The CC must be at least POWER_UP at 3.3 V and V at 1.3 V. CCP CC Datasheet 125 ...

  • Page 126

    ... I Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux* on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC =1 ...

  • Page 127

    ... MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC = 1 ...

  • Page 128

    ... MHz Notes: 1. Typical current ICC and ICCP are not tested. Typical currents were measured on the Intel IXCDP1100 Development Platform at room temperature using typical SKU silicon samples. A SmartBits* tester was used in a router application running Linux on the KIXDP425BD. Two Ethernet NPEs, and two Ethernet controller PCI cards were used in this router application. Typical case power supply voltages VCC = 1 ...