PRIXP425ABD Intel, PRIXP425ABD Datasheet - Page 27

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PRIXP425ABD

Manufacturer Part Number
PRIXP425ABD
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425ABD

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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Datasheet—Intel
2.2.4
2.2.5
June 2007
Document Number:
When an instruction pre-fetch misses in the ITLB, the IMMU invokes an automatic
table-walk mechanism that fetches an associated descriptor from memory and loads it
into the ITLB. The descriptor contains information for logical-to-physical address
translation, memory-access permissions, memory-domain identifications, and
attributes governing operation of the I-cache. The IMMU then continues the instruction
pre-fetch by using the address translation just entered into the ITLB. When an
instruction pre-fetch hits in the ITLB, the IMMU continues the pre-fetch using the
address translation already resident in the ITLB.
Access permissions for each of up to 16 memory domains can be programmed. When
an instruction pre-fetch is attempted to an area of memory in violation of access
permissions, the attempt is aborted and a pre-fetch abort is sent to the Intel XScale
processor for exception processing. The IMMU and DMMU can be enabled or disabled
together.
Data Memory Management Unit (DMMU)
For data fetches, the DMMU controls logical-to-physical address translation, memory-
access permissions, memory-domain identifications, and attributes (governing
operation of the data cache or mini-data cache and write buffer). The DMMU contains a
32-entry, fully associative data-translation, look-aside buffer (DTLB) that has a round-
robin replacement policy. DTLB entries 0 through 30 can be locked.
When a data fetch misses in the DTLB, the DMMU invokes an automatic table-walk
mechanism that fetches an associated descriptor from memory and loads it into the
DTLB. The descriptor contains information for logical-to-physical address translation,
memory-access permissions, memory-domain identifications, and attributes (governing
operation of the D-cache or mini-data cache and write buffer).
The DMMU continues the data fetch by using the address translation just entered into
the DTLB. When a data fetch hits in the DTLB, the DMMU continues the fetch using the
address translation already resident in the DTLB.
Access permissions for each of up to 16 memory domains can be programmed. When a
data fetch is attempted to an area of memory in violation of access permissions, the
attempt is aborted and a data abort is sent to the Intel XScale
processing.
The IMMU and DMMU can be enabled or disabled together.
Instruction Cache (I-Cache)
The I-cache can contain high-use, multiple-code segments or entire programs, allowing
the Intel XScale
processor stalls caused by multi-cycle accesses to external memory.
The 32-Kbyte I-cache is 32-set/32-way associative, where each set contains 32 ways
and each way contains a tag address, a cache line of instructions (eight 32-bit words
and one parity bit per word), and a line-valid bit. For each of the 32 sets, 0 through
28 ways can be locked. Unlocked ways are replaceable via a round-robin policy.
The I-cache can be enabled or disabled. Attribute bits within the descriptors, contained
in the ITLB of the IMMU, provide some control over an enabled I-cache.
When a needed line (eight 32-bit words) is not present in the I-cache, the line is
fetched (critical word first) from memory via a two-level, deep-fetch queue. The fetch
queue allows the next instruction to be accessed from the I-cache, but only when its
data operands do not depend on the execution results of the instruction being fetched
via the queue.
®
252479-007US
IXP42X product line and IXC1100 control plane processors
®
processor access to instructions at core frequencies. This prevents
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
®
processor for exception
Datasheet
®
27

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