PRIXP425ABD Intel, PRIXP425ABD Datasheet - Page 42

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PRIXP425ABD

Manufacturer Part Number
PRIXP425ABD
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP425ABD

Core Operating Frequency
533MHz
Package Type
BGA
Pin Count
492
Mounting
Surface Mount
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Operating Temperature Classification
Commercial
Lead Free Status / Rohs Status
Compliant

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Functional Signal Descriptions
Table 13.
Table 14.
June 2007
42
Expansion Bus Interface (Sheet 2 of 2)
UART Interfaces (Sheet 1 of 2)
EX_RD_N
EX_CS_N[7:0]
EX_DATA[15:0]
EX_IOWAIT_N
EX_RDY[3:0]
††
RXDATA0
TXDATA0
CTS0_N
††
Name
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs
that have this signal pulled low.
Power
or Sys
Reset
Reset
H
Z
Z
Power
or Sys
Reset
Reset
Z
Z
Z
H
H
Reset
VI/PE
Post
VO
VI
Reset
Post
Type
1
1
0
H
H
O
I
I
Type
I/O
UART serial data input to High-Speed UART Pins.
Should be pulled high
UART serial data output. The TXD signal is set to the MARKING (logic 1) state upon a reset operation. High-Speed Serial
UART Pins.
UART CLEAR-TO-SEND input to High-Speed UART Pins.
When logic 0, this pin indicates that the modem or data set connected to the UART interface of the processor is ready to
exchange data. The CTS_N signal is a modem status input whose condition can be tested by the processor.
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
O
O
I
I
Table 5 on page
Table 5 on page
Intel-mode read strobe / Motorola-mode read-not-write (EXPB_MOT_RNW) / TI mode read-not-write
(TI_HR_W_N).
External chip selects for expansion bus.
Expansion-bus, bidirectional data
Data ready/acknowledge from expansion-bus devices. Expansion-bus access is halted when an external device
sets EX_IOWAIT_N to logic 0 and resume from the halted location once the external device sets EX_IOWAIT_N to
logic 1. This signal affects accesses that use EX_CS_N[7:0] when the chip select is configured in Intel- or
Motorola-mode of operation.
Should be pulled high through a 10-KΩ resistor when not being utilized in the system.
HPI interface ready signals. Can be configured to be active high or active low. These signals are used to halt
accesses using Chip Selects 7 through 4 when the chip selects are configured to operate in HPI mode. There is
one RDY signal per chip select. This signal only affects accesses that use EX_CS_N[7:4].
Should be pulled high
• Chip selects 0 through 7 can be configured to support Intel or Motorola bus cycles.
• Chip selects 4 through 7 can be configured to support TI HPI bus cycles.
30.
30.
††
through a 10-KΩ resistor when not being utilized in the system.
††
though a 10-KΩ resistor when not being utilized in the system.
Intel
®
IXP45X and Intel
Description
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US

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