PRIXP425BC 869083 Intel, PRIXP425BC 869083 Datasheet - Page 38

• Manufacturer Part Number: PRIXP425BC 869083
• Manufacturer: Intel

Specifications of PRIXP425BC 869083

• Core Operating Frequency: 400MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Table 9.
Intel
Datasheet
38
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
High-Speed, Serial Interface 0
HSS_TXFRAME0
HSS_TXDATA0
HSS_TXCLK0
HSS_RXFRAME0
HSS_RXDATA0
HSS_RXCLK0
†
††
Name
For a legend of the Type codes, see
For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the
system. No change is required to existing designs that have this signal pulled low.
Power
or Sys
Reset
Reset
Z
Z
Z
Z
Z
Z
Reset
Post
VI
Z
Z
Z
Z
Z
Intel
Type
O/D
I/O
I/O
I/O
I/O
I
®
IXP42X product line and IXC1100 control plane processors
†
Table 5 on page
The High-Speed Serial (HSS) transmit frame signal can be
configured as an input or an output to allow an external
source become synchronized with the transmitted data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high
utilized in the system.
Transmit data out. Open Drain output.
Must be pulled high with a 10-KΩ resistor to V
The High-Speed Serial (HSS) transmit clock signal can be
configured as an input or an output. The clock can be a
frequency ranging from 512 KHz to 8.192 MHz. Used to clock
out the transmitted data. Configured as an input upon reset.
Frame sync and data can be selected to be generated on the
rising or falling edge of the transmit clock.
Should be pulled high
utilized in the system.
The High-Speed Serial (HSS) receive frame signal can be
configured as an input or an output to allow an external
source to become synchronized with the received data. Often
known as a Frame Sync signal. Configured as an input upon
reset.
Should be pulled high
utilized in the system.
Receive data input. Can be sampled on the rising or falling
edge of the receive clock.
Should be pulled high
being utilized in the system.
The High-Speed Serial (HSS) receive clock signal can be
configured as an input or an output. The clock can be from
512 KHz to 8.192 MHz. Used to sample the received data.
Configured as an input upon reset.
Should be pulled high
utilized in the system.
33.
††
††
††
††
††
with a 10-KΩ resistor when not being
with a 10-KΩ resistor when not being
with a 10-KΩ resistor when not being
with a 10-KΩ resistor when not being
through a 10-KΩ resistor when not
Description
Document Number: 252479-006US
CCP
.
August 2006