PRIXP420ABB 885158

Manufacturer Part NumberPRIXP420ABB 885158
ManufacturerIntel
PRIXP420ABB 885158 datasheet
 

Specifications of PRIXP420ABB 885158

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Intel
IXP42X Product Line of
Network Processors and IXC1100
Control Plane Processor
Hardware Design Guidelines
December 2007
Document Number:
252817-008US
December 2007

PRIXP420ABB 885158 Summary of contents

  • Page 1

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines December 2007 Document Number: 252817-008US December 2007 ...

  • Page 2

    ... Current characterized errata are available on request. Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an order number and are referenced in this document, or other Intel literature, may be obtained by calling 1-800-548- 4725 visiting Intel’ ...

  • Page 3

    ... HSS Interface Block Diagram ................................................................... 44 3.10 PCI Interface .................................................................................................... 44 3.10.1 PCI Interface Signals .............................................................................. 45 3.10.2 PCI Interface Block Diagram .................................................................... 47 3.10.3 Design Notes ......................................................................................... 47 3.11 JTAG Interface .................................................................................................. 48 December 2007 Document Number: 252817-008US ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 3 ...

  • Page 4

    ... Expansion Bus Interface .....................................................................................86 A.7.1 Expansion Bus Configuration Strappings ....................................................87 A.8 UART Interface ..................................................................................................88 ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 4 ® Intel IXP42X product line and IXC1100 control plane processors—Contents December 2007 Document Number: 252817-008US ...

  • Page 5

    ... Power Filtering Diagram................................................................................. 92 CCPLL1 36 V Power Filtering Diagram................................................................................. 93 CCPLL2 37 V Power Filtering Diagram ................................................................................ 93 CCOSCP 38 V Power Filtering Diagram ................................................................................. 94 CCOSC December 2007 Document Number: 252817-008US , V Pin Requirements .............................................. 92 CCOSCP CCOSC ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 5 ...

  • Page 6

    ... High-Speed, Serial Interface 0 ...................................................................................83 25 High-Speed, Serial Interface 1 ...................................................................................83 26 MII Interfaces ..........................................................................................................84 27 UTOPIA-2 Interface ..................................................................................................85 28 Expansion Bus Interface ............................................................................................86 29 Expansion Bus Configuration Register 0 .......................................................................87 30 Setting the Intel XScale 31 UART Interfaces .......................................................................................................88 32 USB Interface ..........................................................................................................89 33 Oscillator Interface ...................................................................................................89 34 GPIO Interface .........................................................................................................90 35 JTAG Interface .........................................................................................................90 36 System Interface ...

  • Page 7

    ... Added information for Intel IXP420 Network Processor variants. Updated clock references from 33.333MHz to 33.33MHz as specified in the Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Datasheet. Updated JTAG signal descriptions. Improved guidelines in Sections and 7. Other minor updates throughout the document ...

  • Page 8

    ... Intel ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 8 ® IXP42X product line and IXC1100 control plane processors—Revision History December 2007 Document Number: 252817-008US ...

  • Page 9

    ... Processor. Information on the generic hardware interface, PCB, and bus topologies are also included. Design recommendations are necessary to meet the timing and signal quality specifications. The guidelines recommended in this document are based on experience and simulation work done at Intel while developing the Intel Platform. These recommendations are subject to change. 1.1 About this Document This document is intended for hardware and systems designers who are experienced with systems and board design ...

  • Page 10

    ... PC133 SDRAM Specification UTOPIA Level 2 Specification, Revision 1.0 IEEE 802.3 Specification IEEE 1149.1 Specification 2 I C-Bus Specification from Philips Semiconductors* Note: For Intel documentation, see the Intel Technical Documentation Center, available at http://www.intel.com/products/index.htm. Acronyms and Abbreviations 1.3 Acronym or Abbreviation AHB ATM EMI ...

  • Page 11

    ... Microarchitecture and the internal components are clocked from an internal PLL. The internal and external interfaces use a 66/133-MHz, 32-bit data bus; a 32-bit address bus; and control signals that enable the interface between the Intel XScale Microarchitecture and peripheral logic to optimize performance. 1.5 Key Features ® ...

  • Page 12

    ... Expansion interface — 24-bit address — 16-bit data — Eight programmable chip selects — Supports Intel and Motorola* microprocessor style bus cycles • Multiplexed-style bus cycles • Simplex-style bus cycles — Texas Instruments* DSPs supporting HPI-8 and HPI-16 bus cycles • ...

  • Page 13

    ... Supports connection to CODEC/SLICs — Eight HDLC Channels Figure 1 illustrates the major internal components of the IXP42X product line and IXC1100 control plane processors. Refer to the Intel Plane Processor Datasheet for complete feature list and block diagram description. December 2007 Document Number: 252817-008US ® ...

  • Page 14

    ... IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 14 ® Intel IXP42X product line and IXC1100 control plane processors—Introduction HSS-W UTOPIA 2 Not for Intel ® IXP420 and IXP422 Network Processors and Intel ® IXC1100 Control Plane Processor Voi ...

  • Page 15

    ... This process technology — along with numerous, dedicated-function peripheral interfaces and many features with the Intel XScale processor — addresses the needs of many system applications and helps reduce system costs. The processors can be configured to meet many system application and implementation needs ...

  • Page 16

    ... Table 1 shows the memory map of peripherals connected to the AHB. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 16 IXP42X product line and IXC1100 control plane processors—System Architecture ...

  • Page 17

    ... MB and the Expansion Bus can be accessed starting at address 5000_0000. The largest SDRAM memory size supported by the Intel and IXC1100 Control Plane Processor is 256 Mbytes. The actual memory implemented in any given configuration will be aliased (repeated) to fill the 1-Gbyte SDRAM address space. Due to aliasing, all of the SDRAM will be accessible even when the Expansion Bus occupies the lowest 256 Mbytes of address space ...

  • Page 18

    ... Intel ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 18 IXP42X product line and IXC1100 control plane processors—System Architecture § § December 2007 Document Number: 252817-008US ...

  • Page 19

    ... General Hardware Design Considerations This chapter contains information on how to implement and interface the SDRAMs, flash, SRAM, Ethernet PHYs, UART and other peripherals to the Intel Line of Network Processors and IXC1100 Control Plane Processor. This chapter’s signal-definition tables list pull-up and pull-down resistor recommendations that are required when the particular enabled interface is not being used in the application ...

  • Page 20

    ... PC133 of SDRAM memory. Table 3. SDRAM Memory Types SDRAM Technology 64 Mbit Note: The 32 and * devices have not been fully validated by Intel. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 20 Type* ...

  • Page 21

    ... SDRAM Technology 128 Mbit 256 Mbit 512 Mbit Note: The 32 and * devices have not been fully validated by Intel. Figure 3, Figure 4, and processors’ memory bus. The figures do not include any termination resistors that may be needed. For best signal integrity results the designer may perform simulations. ...

  • Page 22

    ... SDM_RAS_N SDM_CAS_N SDM_WE_N SDM__DQM[3:0] SDM_BA[1:0] SDM_CKE SDM_CLKOUT ® Intel IXP42X Product Line and IXC 1100 Control Plane Processors ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 22 BANK0 SMD_DATA[31:0] DQ[31:0] A[10:0] SDM_CS_N0 CS# RAS# CAS# WE# ...

  • Page 23

    ... General Hardware Design Considerations—Intel plane processors Figure 4 illustrates how the IXP42X product line and IXC1100 control plane processors’ interfaces to one bank (2 Chips) of the PC133 SDRAM using the (128-Mbit (256-Mbit (512-Mbit). Figure 4. Single Bank SDRAM System Block Diagram (x16 Devices) ...

  • Page 24

    ... Software issues one NOP cycle after the 1ms SDRAM device deselect. A NOP is accomplished by setting the SDRAM Instruction (SDR_IR) Register to 011. The memory controller asserts SDM_CKE with the NOP. • Software pauses 200 µs after the NOP. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 24 BANK 0 ...

  • Page 25

    ... The IXP42X product line and IXC1100 control plane processors’ expansion bus supports a variety of types and speeds of I/O accesses and is specifically designed for compatibility with Intel and Motorola* microprocessor style bus cycles and the Texas Instruments* DSP standard Host-Port Interfaces (HPI). ...

  • Page 26

    ... TI*-mode data strobe (TI_HDS1_N). Intel-mode read strobe / Motorola-mode read-not-write O (EXPB_MOT_RNW mode read-not-write (TI_HR_W_N). External chip selects for expansion bus. • Chip selects 0 through 7 can be configured to support Intel or O Motorola bus cycles. • Chip selects 4 through 7 can be configured to support TI HPI bus cycles. ...

  • Page 27

    ... Column 1 of the part from the factory. Columns 2, 3, and 4 denote the values captured on the Expansion-Bus address bits at the de-assertion of reset. Column 5 represents the speed at which the Intel XScale processor speed will operate. 3.2.2.1 User-Configurable Field ® ...

  • Page 28

    ... Flash Interface Figure 6 illustrates how the boot ROM is connected through the expansion bus. The flash used in the block diagram is the Intel 28F128J3D. The boot ROM address space supports up to 16-Mbyte (128-Mbit) of flash. The boot ROM maps to the Intel XScale (reset), the Intel fetch and execute instructions from address 0x00 ...

  • Page 29

    ... General Hardware Design Considerations—Intel plane processors Figure 7. Expansion Bus SRAM Interface EX_DATA[15: 0] EX_ADDR[23:0] Intel IXP42X Product Line and IXC1100 Control Plane Processors 3.2.5 Design Notes The IXP42X product line and IXC1100 control plane processors’ expansion bus I/O buffers are designed to support up to eight loads, but the devices on the bus may not be able to quickly drive the large load ...

  • Page 30

    ... Mbps. To allow full modem control on the fast UART connection, system designers have to use four GPIO pins to generate the RS-232 signals (DTR, DSR, RI, and DCD) that are not available on the processor high-speed UART interfaces. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 30 ...

  • Page 31

    ... General Hardware Design Considerations—Intel plane processors Figure 8. Fast UART Interface UART_CTS_N0 UART_RTS_N0 UART_RXDATA0 UART_TXDATA0 GPIO ® Intel IXP42X Product Line and IXC1100 Control Plane Processors 3.3.3 Console UART The Console UART on the IXP42X product line and IXC1100 control plane processors has the same features as the High-Speed UART ...

  • Page 32

    ... TX and RX MII interface (ETH_TX_CLK, ETH_RX_CLK) for each Ethernet PHY are expected to be supplied from onboard oscillators or PLL. General LAN routing guidelines can be found in Considerations” on page Specification. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 32 RS-232 Transceiver Section 6.3.2, “ ...

  • Page 33

    ... Management data clock. Management data interface clock used clock the MDIO signal as an output and sample the MDIO as an input. The ETH_MDC is an input on power up and can be ETH_MDC I/O configured output through an Intel API, which can be found in the Intel Software Programmer’s Guide. Externally supplied transmit clock. • 25 MHz for 100-Mbps operation ...

  • Page 34

    ... Should be pulled high through a 10-kΩ resistor when not being used in the system. Type Note: For explanations of the ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 34 Description column abbreviations, see Table 21 on page Considerations 81 ...

  • Page 35

    ... General Hardware Design Considerations—Intel plane processors 3.4.2 MII Block Diagram Figure 10. MII Block Diagram ® Intel IXP42X Product Line and IXC 1100 Control Plane Processors ETH_RXD[3:0] ETH_TXD[3:0] ETH_TXCLK ETH_RXDV ETH_RXCLK ETH_COL ETH_CRS ETH_INT_N ETH_TXEN ETH_MDC ETH_MDIO MII Interface 3.5 GPIO Interface ...

  • Page 36

    ... I EEPROM, 7-bit addressing mode (Philips* PC8582C-2T/03) using two processors’ GPIO pins (GPIO6 and GPIO7). ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 36 General-purpose input/output pins. May be configured as an input or an output. ...

  • Page 37

    ... The official I C-bus protocol supports three modes of transfer rates: • Standard Mode — 100 Kbps • Fast Mode — 400 Kbps • High Speed Mode — 3.4 Mbps More information is available in the Intel Plane Processors: I December 2007 Document Number: 252817-008US ® ...

  • Page 38

    ... Signals Table 9. Signals Name USB_DPOS USB_DNEG Note: For explanations of the ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 38 2 C-Bus Specification on determining the Section 6.3.3, “USB Considerations” on Type* Description I/O Positive signal of the differential USB receiver/driver. ...

  • Page 39

    ... General Hardware Design Considerations—Intel plane processors 3.7.2 USB Interface Figure 12. USB Interface ® Intel IXP42X Product Line and IXC1100 Control Plane Processors 24-27 Ω USB_DPOS (D+) USB Driver Port 24-27 Ω USB_DNEG (D-) 3.7.3 Design Notes The integrated USB in the IXP42X product line and IXC1100 control plane processors is an USB-device-only controller, and it can get its power from the bus or supplies its power: bus or self-powered devices ...

  • Page 40

    ... ATM cells, CRC checking/generation, and transfer of data to/from memory. This allows parallel processing of data traffic on the UTOPIA-2 interface, off- loading processor overhead required by the Intel XScale The IXP421 and IXP425 processors are compliant with the ATM Forum, UTOPIA Level-2 Specification, Revision 1.0; for optimal design results recommended to follow the guidelines of the Specification ...

  • Page 41

    ... General Hardware Design Considerations—Intel plane processors Table 10. Interface Signals (Sheet Signal I/O* UTOPIA Input Data flow control input signal. Also known as RXEMPTY/CLAV. Used to inform the cell-level flow control in an MPHY environment, RxClav is an active-high tri-stateable signal from the MPHY to ATM layer. The UTP_IP_FCI, which is connected to multiple MPHY devices, will see logic high generated by the PHY, one clock after the given PHY address is asserted, when a full cell can be received by the PHY ...

  • Page 42

    ... HSS interface. The HSS can directly interface to SLIC/CODEC devices for voice applications, to serial DSL framers and also support the serial protocols, including T1, E1, and MVIP. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 42 ...

  • Page 43

    ... General Hardware Design Considerations—Intel plane processors 3.9.1 Interface Signals Name HSS_TXFRAME1 HSS_TXDATA1 HSS_TXCLK1 HSS_RXFRAME1 HSS_RXDATA1 HSS_RXCLK1 HSS_TXFRAME0 HSS_TXDATA0 HSS_TXCLK0 Note: For explanations of the December 2007 Document Number: 252817-008US ® IXP42X product line and IXC1100 control Type The High-Speed Serial (HSS) transmit frame signal can be configured as an input or an output to allow an external source to be synchronized with the transmitted data ...

  • Page 44

    ... PCI devices. As indicated in Figure General PCI routing guidelines can be found in page 75. For more detailed information, see the PCI Local Bus Specification, Rev. 2.2. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 44 CS SLIC CODEC DTX ...

  • Page 45

    ... General Hardware Design Considerations—Intel plane processors 3.10.1 PCI Interface Signals Table 11. PCI Bus Signals (Sheet Name PCI_AD[31:0] PCI_CBE_N[3:0] PCI_PAR PCI_FRAME_N PCI_TRDY_N PCI_IRDY_N PCI_STOP_N PCI_PERR_N PCI_SERR_N PCI_DEVSEL_N PCI_IDSEL PCI_REQ_N[3:1] Note: For explanations of the December 2007 Document Number: 252817-008US ® IXP42X product line and IXC1100 control ...

  • Page 46

    ... PCI_REQ_N[0] PCI_GNT_N[3:1] PCI_GNT_N[0] PCI_INTA_N PCI_CLKIN Note: For explanations of the ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 46 Type* Description PCI arbitration request: • When configured as an input (PCI arbiter enabled), the internal PCI arbiter will allow an agent to request the PCI bus. ...

  • Page 47

    ... General Hardware Design Considerations—Intel plane processors 3.10.2 PCI Interface Block Diagram Figure 15. PCI Interface ® Intel IXP42X Product Line and IXC1100 Control Plane Processors When one of the IXP42X product line and IXC1100 control plane processors is host, it may interface to four PCI slots at 33 MHz or two PCI slots at 66 MHz. The limitation to two slots at 66 MHz is due to load requirements to maintain signal integrity at the higher frequency ...

  • Page 48

    ... Table controller, instruction register, boundary-scan register, bypass register, device identification register, and data-specific registers. These are described in the Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Developer’s Manual. The IXP42X product line and IXC1100 control plane processors may be controlled ...

  • Page 49

    ... General Hardware Design Considerations—Intel plane processors The interfaces require oscillators on the board. • Processors’ system clock – 33.33 MHz • PCI host clock – 33 MHz and 66 MHz selectable • Expansion bus clock – This expansion bus clock may be driven through GPIO15 or using an external oscillator ...

  • Page 50

    ... Oscillator Connection Description 1 power supply input pins used for the internal logic of the Intel Line of Network Processors and IXC1100 Control Plane Processor 3.3-V power supply input pins used for the peripheral (I/O) logic of the IXP42X product line and IXC1100 control plane processors. ...

  • Page 51

    ... Power Supply Requirements The main power supply domains for the IXP42X product line and IXC1100 control plane processors are 1.3 V (VCC) for the Intel XScale signaling voltage. 3.13.2 +3 suggested that the +3.3-V supply tolerance is +/-5% and a maximum current and is provided by an on-board DC-DC switch-mode voltage regulator ...

  • Page 52

    ... Figure 18. Reset Timings V CCP V CC PLL_LOCK PWRON_RESET_N RESET_IN_N EX_ADDR[23:0] EX_ADDR[23:0]-Pull Up/Down ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 52 T POWER _UP TIME CFG Settings To Be Captured CFG Settings To Be Captured RELEASE_RST_N PLL_LOCK ...

  • Page 53

    ... General Hardware Design Considerations—Intel plane processors Table 15. Reset Timings Table Parameters Symbol T RELEASE_PWRON_RST_N T RELEASE_RESET_IN_N T PLL_LOCK T EX_ADDR_SETUP T EX_ADDR_HOLD T WARM_RESET Notes RELEASE_PWRON_RST_N 2. The expansion bus address is captured during RESET_IN_N signal transition from low to high. When a programmable-logic device is used to drive the EX_ADDR signals, instead of pull-downs, the signals must be held stable until the PLL_LOCK goes high ...

  • Page 54

    ... Intel IXP42X product line and IXC1100 control plane processors—General Hardware Design ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 54 Considerations December 2007 Document Number: 252817-008US ...

  • Page 55

    ... IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor have a 492-ball, PBGA package for commercial temperature applications and a pin-for-pin-compatible, 492-ball, PBGA with a drop-in heat spreader for extended temperature applications. For detailed signal descriptions, see the Intel Processors and IXC1100 Control Plane Processor Datasheet. Figure 19. 492-Ball PBGA Package 0.127 A 35.00 ± ...

  • Page 56

    ... Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 56 ® IXP42X product line and IXC1100 control plane processors—PBGA Package ® Intel IXP42X Product Line and IXC1100 Control Plane Processors § § SDM_DATA[31:0] SDM_ADDR[12:0] SDM_CLKOUT ...

  • Page 57

    ... General PCB Guide—Intel IXP42X product line and IXC1100 control plane processors 5.0 General PCB Guide 5.1 PCB Overview Beginning with components selection, this chapter presents general PCB guidelines. In cases where it is too difficult to adhere to a guideline, engineering judgment must be used. The methods are listed below as simple DOs and DON’ ...

  • Page 58

    ... Manufactured by virtually all printed-circuit-board vendors — Disadvantages: • Poor routing density • Uncontrolled signal trace impedance ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 58 IXP42X product line and IXC1100 control plane processors—General PCB Guide ...

  • Page 59

    ... General PCB Guide—Intel IXP42X product line and IXC1100 control plane processors • Lack of power/ground planes, resulting in unacceptable cross-talk • Relatively high-impedance power distribution circuitry, resulting in noise on the power and ground rails • High-speed circuits require multi-layer printed circuit boards; ...

  • Page 60

    ... Trace width: 5 mils • Signal Layers (1/2 oz. Cu) • Power Layer (1 oz. Cu) • Ground (GND) Layer (1 oz. Cu) ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 60 IXP42X product line and IXC1100 control plane processors—General PCB Guide 4 ...

  • Page 61

    ... General Layout and Routing Guide 6.1 Overview This chapter provides routing and layout guides for the Intel Network Processors and IXC1100 Control Plane Processor-based hardware and systems design. The high-speed clocking required when designing with the processors requires special attention to signal integrity. In fact highly recommended that the board design be simulated to determine optimum layout for signal integrity ...

  • Page 62

    ... PGA or BGA components. Figure 25. Poor Design Practice for VIA Placement ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 62 25 mils min show good and poor design practices for via placement on ...

  • Page 63

    ... General Layout and Routing Guide—Intel processors Figure 26. Pad-to-Pad Clearance of Passive Components to a PGA or BGA 6.3 General Routing Guides This section details general routing guidelines for connecting the IXP42X product line and IXC1100 control plane processors. The specific details on the layout of the PCI, 133-MHz memory interface are discussed in later sections ...

  • Page 64

    ... Provide ground vias next to every signal via explicitly for the purpose of letting return currents jump between layers. • Select type of grounding: single- or multi-point ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 64 VIAs ...

  • Page 65

    ... General Layout and Routing Guide—Intel processors — Use single-point grounding for low-frequency applications (audio, etc.) with clock rates of 1 MHz or lower. — Use multi-point grounding for high-frequency circuits with clock rates of 1 MHz or higher. 6.3.1 Clock Signal Considerations • Provide return paths of board power and ground close to clock traces. ...

  • Page 66

    ... For LAN designs, the length of the differential traces between the transformer’s solder pads to the PHY’s transmit and receive solder pads should preferably be less than three inches, and never more than four inches. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 66 ...

  • Page 67

    ... General Layout and Routing Guide—Intel processors • For LAN designs, the length of the differential traces between the RJ connector solder pads to transformer’s transmit and receive solder pads should preferably be less than three inches, and never more than four inches. • LAN differential traces must be impedance matched to the wire on the connector side of the transformer and the terminating resistance on the other side of the transformer. For Ethernet, the wire side impedance is approximately 100 Ω ...

  • Page 68

    ... It is strongly recommended that good electromagnetic interference (EMI) design practices be followed when designing with the IXP42X product line and IXC1100 control plane processors. • Information on spread-spectrum clocking is available in Intel of Network Processors and IXC1100 Control Plane Processor: Spread-Spectrum Clocking to Reduce EMI Application Note. ...

  • Page 69

    ... General Layout and Routing Guide—Intel processors • Carefully match the type and value of capacitor to the range of frequencies it must bypass (i.e., tantalum capacitors are more effective at higher frequencies than aluminum electrolytic capacitors, and capacitors of different values are effective at different frequencies). • Place all components associated with one clock trace closely together. This reduces the trace length and reduces radiation ...

  • Page 70

    ... Place one 1000-pF capacitor for each power pin on clock buffers and clock synthesizer components. • Use the right value capacitor — Use 10-pF ceramic SMT capacitors for decoupling clock signals for EMI control. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 70 Guide ...

  • Page 71

    ... General Layout and Routing Guide—Intel processors — Use 470-pF or 1,000-pF SMT ceramic capacitors for decoupling all connector pins for EMI control. — Use 0.1-µF SMT ceramic capacitors for general IC decoupling and ESD protection. X7R or X7S dielectric is preferred for ceramic capacitors due to their superior temperature and aging characteristics ...

  • Page 72

    ... Intel IXP42X product line and IXC1100 control plane processors—General Layout and Routing ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 72 Guide December 2007 Document Number: 252817-008US ...

  • Page 73

    ... Critical Routing Topologies—Intel IXP42X product line and IXC1100 control plane processors 7.0 Critical Routing Topologies This chapter contains information for recommended trace lengths, size, and routing guidelines for the PC133 SDRAM and PCI bus. 7.1 PC133 SDRAM Topologies ® ...

  • Page 74

    ... Clock signals must have 1-4 SDRAM loads with 3.3-pF cap load • PCB Impedance: 50 Ω ± 10% Figure 29 shows the PC 133 SDRAM clock topology. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 74 Trace (Mils) ...

  • Page 75

    ... Critical Routing Topologies—Intel IXP42X product line and IXC1100 control plane processors Figure 29. SDRAM Clock Topology Topology 1 Topology 2 Table 17. SDRAM Clock Routing Guidelines Signal SDM_CLK SDM_CLK • Clocks must be routed with as much of the trace on inner signal layer as possible. • Clocks on the inner layer have a 5-mil ground trace surrounding them with vias stitched to ground at 0.5” ...

  • Page 76

    ... Nominal Trace Width Nominal Trace Separation Spacing to Other Groups Trace length A Trace length B Trace length C Trace length D Maximum VIAS Count per Signal ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 76 PCI Slot Routing Guidelines ...

  • Page 77

    ... Critical Routing Topologies—Intel IXP42X product line and IXC1100 control plane processors Figure 31. PCI Address/Data Topology (PCI Bridge to cPCI Bridge Connector) Table 19. PCI Address/Data Routing Guidelines Parameter Signal Group Topology Reference Plane Ground Characteristic Trace Impedance Nominal Trace Width Nominal Trace Separation ...

  • Page 78

    ... The capacitor should be placed not more that 0.25 inches from the point the signals cross the split. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines ...

  • Page 79

    ... Critical Routing Topologies—Intel IXP42X product line and IXC1100 control plane processors 7.2.3 Signal Loading Shared PCI signals must be limited to one load on each of the PCI slots. Any violation of expansion board or add-on device trace length or loading limits compromises system- signal integrity. ...

  • Page 80

    ... Intel IXP42X product line and IXC1100 control plane processors—Critical Routing Topologies ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 80 December 2007 Document Number: 252817-008US ...

  • Page 81

    ... The following set of tables provide design considerations for the various interfaces of a design. Each table describes one of those portions and is titled accordingly. Contact your Intel field representative in the event of questions or issues regarding the interpretation of the information in these tables. Listed in the signal definition tables — starting at page 82 — ...

  • Page 82

    ... For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs that have this signal pulled low. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 82 ® ...

  • Page 83

    ... Design Checklist—Intel IXP42X product line and IXC1100 control plane processors Table 23. PCI Interface (Sheet Name PCI_GNT_N[3:1] PCI_GNT_N[0] PCI_INTA_N PCI_CLKIN † For a legend of the †† For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system ...

  • Page 84

    ... For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system. No change is required to existing designs that have this signal pulled low. ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 84 ® ...

  • Page 85

    ... Design Checklist—Intel IXP42X product line and IXC1100 control plane processors Table 26. MII Interfaces (Sheet Name ETH_MDIO ETH_MDC ETH_TXCLK1 ETH_TXDATA1[3:0] ETH_TXEN1 ETH_RXCLK1 ETH_RXDATA1[3:0] ETH_RXDV1 ETH_COL1 ETH_CRS1 † For a legend of the †† For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system ...

  • Page 86

    ... Input clock signal used to sample all expansion interface inputs I and clock all expansion interface outputs. GPIO15 maybe used as the clock source. Used in Intel and Motorola* multiplexed modes of operation external circuitry needed. Expansion-bus address used as an output for data accesses over the expansion bus. Also, used as an input during reset to capture device configuration ...

  • Page 87

    ... December 2007 Document Number: 252817-008US † Type Recommendation External chip selects for expansion bus. Chip selects 0 through 7 can be configured to support Intel or O Motorola bus cycles. Chip selects 4 through 7 can be configured to support TI* HPI bus cycles. I/O No external circuitry needed, Should be pulled high through a 10-KΩ resistor when not being I utilized in the system ...

  • Page 88

    ... MHz 266 MHz 266 MHz Note that the Intel XScale processor can operate at slower speeds than the factory programmed speed setting. This is done by placing a value on Expansion bus address bits 23,22,21 at the de-assertion of RESET_IN_N and knowing the speed grade of the part from the factory. Column 1 of the factory ...

  • Page 89

    ... Design Checklist—Intel IXP42X product line and IXC1100 control plane processors Table 31. UART Interfaces (Sheet Name Type CTS1_N I RTS1_N O † For a legend of the †† For new designs, this signal should be pulled high with a 10-KΩ resistor when not being utilized in the system ...

  • Page 90

    ... BYPASS_CLK SCANTESTMODE_N RESET_IN_N PWRON_RESET_N HIGHZ_N PLL_LOCK † For a legend of the ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 90 ® IXP42X product line and IXC1100 control plane processors—Design Checklist † Recommendation †† Should be pulled high using a 10-KΩ ...

  • Page 91

    ... Design Checklist—Intel IXP42X product line and IXC1100 control plane processors Table 36. System Interface (Sheet Name RCOMP † For a legend of the A.13.1 RCOMP Pin Requirements Figure 34 shows the requirements for the RCOMP pin. Figure 34. RCOMP Pin External Resistor Requirements A.14 Power Interface Table 37 ...

  • Page 92

    ... Complete? Figure 36 on 81. Pin Requirements V , CCPLL1 CCPLL2 supply pin. Both SS pin and the CCPLL1 V CCPLL1 ® Intel IXP42X Product Line / ® Intel IXC1100 Control Plane V SS Processor B1680-03 supply pin. Both SS pin and the CCPLL2 December 2007 Document Number: 252817-008US ) and ...

  • Page 93

    ... Design Checklist—Intel IXP42X product line and IXC1100 control plane processors Figure 36. V Power Filtering Diagram CCPLL2 1 A.15.3 V Requirement CCOSCP A single 170-nF capacitor must be connected between the V pin of the IXP42X product line and IXC1100 control plane processors. This capacitor value provides both bypass and filtering. ...

  • Page 94

    ... A.16 Common Issues Completing the checklist in schematics prior to manufacturing a system board that implements an Intel Product Line of Network Processors and IXC1100 Control Plane Processor. This section highlights some commonly overlooked issues that deserve extra attention as they could be a “show-stopper” if handled incorrectly. ...

  • Page 95

    ... Designs that need to pass FCC Class B testing may want to consider Spread Spectrum Clocking. For more detailed information, see Intel Processors and IXC1100 Control Plane Processor: Spread-Spectrum Clocking to Reduce EMI Application Note (254028). • For recommendations and guidelines on PCB layout and stackup, signal routing, component selection and placement, and decoupling, refer to the respective chapters of the document ...

  • Page 96

    ... Intel ® Intel IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor Hardware Design Guidelines 96 ® IXP42X product line and IXC1100 control plane processors—Design Checklist December 2007 Document Number: 252817-008US ...