PRIXP420ABD 885159 Intel, PRIXP420ABD 885159 Datasheet - Page 59

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PRIXP420ABD 885159

Manufacturer Part Number
PRIXP420ABD 885159
Description
Manufacturer
Intel
Datasheet

Specifications of PRIXP420ABD 885159

Lead Free Status / Rohs Status
Compliant
General PCB Guide—Intel
December 2007
Document Number: 252817- 008US
An example for a six-layer and eight-layer board is shown below. For stripline (signals
between planes), the stackup should be such that the signal line is closer to one of the
planes by a factor of five or more. Then the trace impedance is controlled
predominantly by the distance to the nearest plane.
the proposed stackup for the six- and eight-layer boards.
• High-speed circuits require multi-layer printed circuit boards;
• Symmetry is essential to keep the board stack-up symmetric about the center
• For best impedance control, have:
• For best noise control, route adjacent layers orthogonally. Avoid layer-to-layer
• Fabrication house must agree on design rules, including:
• The distance between the signal layer and ground (or power) should be minimized
parallelism.
to reduce the loop area enclosed by the return current
— Advantages:
— Disadvantages:
— This minimizes warping
— No more than two signal layers between every power/ground plane pair
— No more than one embedded micro-strip layer under the top/bottom layers
— Trace width, trace separation
— Drill/via sizes
— Use 0.7:1 ratio as a minimum.
• Lack of power/ground planes, resulting in unacceptable cross-talk
• Relatively high-impedance power distribution circuitry, resulting in noise on
• Controlled-impedance traces
• Low-impedance power distribution
• Higher cost
• More weight
• Manufactured by fewer vendors
®
For example: 5-mil traces, 7-mil prepreg thickness to adjacent power/ground
IXP42X product line and IXC1100 control plane processors
the power and ground rails
Intel
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Figure 22
and
Hardware Design Guidelines
Figure 23
illustrate
59

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