PRIXP420ABD 885159 Intel, PRIXP420ABD 885159 Datasheet - Page 75

• Manufacturer Part Number: PRIXP420ABD 885159
• Manufacturer: Intel

Specifications of PRIXP420ABD 885159

• Lead Free Status / Rohs Status: Compliant

Critical Routing Topologies—Intel
Figure 29.
Table 17.
7.2
December 2007
Document Number: 252817-008US
SDRAM Clock Topology
SDRAM Clock Routing Guidelines
PCI Topologies
The IXP42X product line and IXC1100 control plane processors’ PCI controller is
designed and provides a PCI-bus interface that is compliant with the PCI Local Bus
Specification, Rev. 2.2. For more information on the PCI Bus interface, see the PCI
Local Bus Specification, Rev. 2.2.
• Clocks must be routed with as much of the trace on inner signal layer as possible.
• Clocks on the inner layer have a 5-mil ground trace surrounding them with vias
• Clock traces must be 5 mil wide with 15 mil spacing to any other signals.
• All the SDM_CLK trace should be equal in length, and Topology 1 is also
stitched to ground at 0.5” intervals.
recommended for two banks of SDRAM implementation.
SDM_CLK
SDM_CLK
Signal
Topology 2
Topology 1
®
IXP42X product line and IXC1100 control plane processors
SMD_CLK_OUT
SMD_CLK_OUT
Topology
Intel
Pad
Pad
1
2
.
®
IXP42X Product Line of Network Processors and IXC1100 Control Plane Processor
Trace (Mils)
Width
A
A
A
A
5
5
C = 10-22 pF
Spacing
R = 22- 33 Ω ±5%
R = 22- 33 Ω ±5%
R = 22- 33 Ω ±5%
15
15
C = 10-22 pf
C = 10-22 pf
Min
0.2
0.2
A
Trace Lengths (Inches)
B
B
B
B
Max
0.5
0.5
Hardware Design Guidelines
Min
0.1
0.1
M
M
S
D
R
A
S
D
R
A
D
R
M
M
S
A
S
D
R
A
B
B2271-01
Max
4.0
2.0
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