PRIXP423ABD Intel, PRIXP423ABD Datasheet - Page 45

• Manufacturer Part Number: PRIXP423ABD
• Manufacturer: Intel

Specifications of PRIXP423ABD

• Core Operating Frequency: 533MHz
• Package Type: BGA
• Pin Count: 492
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

Functional Signal Descriptions
Table 18.
Table 19.
June 2007
45
JTAG Interface
System Interface
†
BYPASS_CLK
SCANTESTMODE_N
RESET_IN_N
PWRON_RESET_N
†
††
JTG_TRST_N
JTG_TMS
JTG_TDO
JTG_TCK
JTG_TDI
Name
Name
For a legend of the Type codes, see
For a legend of the Type codes, see
IMPORTANT NOTE: When a system-level reset is asserted to the Intel
Processor — either via a power-on reset, a system reset, or a Watchdog-Timer reset — and any interface is in an active transaction (particularly the PCI
bus or expansion bus, but not precluding any interface), an illegal protocol is generated. The behavior of the IXP42X product line and IXC1100 control
plane processors is undefined in this situation and a reset of other attached devices may be required.
Power
or Sys
Reset
Reset
H
H
Z
H
Z
††
Power
or Sys
Reset
Reset
Reset
VI/PE
Z
H
0
0
VI/PE
VI/PE
Post
VO
VI
Reset
VI/PE
Post
Type
VI
VI
VI
O
I
I
I
I
†
Type
Table 5 on page
Table 5 on page
Test mode select for the IEEE 1149.1 JTAG interface.
Input data for the IEEE 1149.1 JTAG interface.
Output data for the IEEE 1149.1 JTAG interface.
Used to reset the IEEE 1149.1 JTAG interface.
The JTG_TRST_N signal must be asserted (driven low) during power-up, otherwise the TAP controller may not be
initialized properly, and the processor may be locked.
When the JTAG interface is not being used, the signal must be pulled low using a 10-KΩ resistor.
Used as the clock for the IEEE 1149.1 JTAG interface.
I
I
I
I
†
Used for test purposes only.
Must be pulled high for normal operation.
Used for test purposes only.
Must be pulled high for normal operation.
Used as a reset input to the device when PWRON_RESET_N is in an inactive state and once power up
conditions are met. Power up conditions include the following:
Signal used at power up to reset all internal logic to a known state after the PLL has achieved a locked
state. The PWRON_RESET_N input is a 1.3-V tolerant only.
— Power supplies reaching a safe stable condition and
— The PLL achieving a locked state
30.
30.
®
Intel
IXP42X Product Line of Network Processors and IXC1100 Control Plane
®
IXP45X and Intel
Description
Description
®
IXP46X Product Line of Network Processors Datasheet
Document Number:
252479-007US