CD4541BCN_NL Fairchild Semiconductor, CD4541BCN_NL Datasheet
CD4541BCN_NL
Specifications of CD4541BCN_NL
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CD4541BCN_NL Summary of contents
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... Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram N.C.—Not connected © 2002 Fairchild Semiconductor Corporation Features Available division ratios 2 Increments on positive edge clock transitions ...
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Truth Table Pin State 0 5 Auto Reset Operating Auto Reset Disabled 6 Timer Operational Master Reset On 9 Output Initially Low Output Initially High after Reset after Reset 10 Single Cycle Mode Recycle Mode Operating Characteristics With Auto Reset ...
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Operating Characteristics Oscillator Circuit Using RC Configuration Logic Diagram V Pin Pin 7 SS (Continued) 3 www.fairchildsemi.com ...
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Absolute Maximum Ratings (Note 2) Supply Voltage ( Input Voltage ( Storage Temperature Range ( Power Dissipation ( Dual-In-Line Small Outline Lead Temperature ( (soldering, 10 seconds) ...
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AC Electrical Characteristics (refer to test circuits Symbol Parameter t Output Rise Time TLH t Output Fall Time THL t t Turn-Off, Turn-On Propagation Delay, PLH, PHL 8 Clock ...
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Test Circuits and Waveforms Power Dissipation Test Circuit and Waveforms (R and C outputs are left open www.fairchildsemi.com Switching Time Test Circuit and Waveforms 6 ...
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Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow Package Number M16A 7 www.fairchildsemi.com ...
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right ...