LMH0070SQ National Semiconductor, LMH0070SQ Datasheet
LMH0070SQ
Specifications of LMH0070SQ
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LMH0070SQ Summary of contents
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... IP which allows the design engineer to quickly develop video applications using the SER/DES products. The SER is pack- aged in a physically small 48 pin LLP package. General Block Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2009 National Semiconductor Corporation LMH0340, LMH0040, LMH0070, LMH0050 Key Specifications ■ ...
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Pin Descriptions Pin Name Type LVDS Input Interface TX[4:0]+ Input, LVDS TX[4:0]- TXCLK+ Input, LVDS TXCLK- Serial Output Interface TXOUT+ Output, CML TXOUT- Output, CML SMBus Interface SDA I/O, LVCMOS SCK Input, LVCMOS SMB_CS Input, LVCMOS Control and Configuration Pins ...
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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage (V ) DD3V3 Supply Voltage (V ) DD2V5 LVCMOS input voltage LVCMOS output voltage Recommended Operating Conditions Parameter Supply Voltage (V -GND) DD3V3 Supply Voltage (V ...
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Symbol Parameter I Input Current IN I Output Short Circuit Current OS LVDS Input Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter V Differential Input High threshold TH V Differential Input Low threshold TL R ...
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SMBus Input Electrical Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter V Data, Clock Input Low Voltage SIL V Data, Clock Input High Voltage SIH I Current through pull-up resistor or SPULLUP current source V Nominal ...
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SDI Output Characteristics — LMH0340 / LMH0040 / LMH0070 Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter V SDI Output Voltage OD DR SDI Output Datarate t SDI Output Rise Time r t SDI Output Fall Time ...
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Device Switching Characteristics Over supply and Operating Temperature ranges unless otherwise specified. Symbol Parameter t Device Lock Time TPLD Note 1: “Absolute Maximum Ratings” are limits beyond which the safety of the device cannot be guaranteed not implied ...
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... SER, the output of the device will be compliant with DVB-ASI, SMPTE 259M-C, SMPTE 292M or SMPTE 424M depending upon the output mode selected. National Semiconductor offers IP in source code format to perform the appropriate formatting of the data, as well as evaluation platforms to assist in the development of target applications ...
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The output driver automatically adjusts its slew rate depending on the input datarate so that it will be in com- pliance with SMPTE 259M, SMPTE292M or SMPTE 424M as appropriate. In addition to output amplitude and rise/fall time specifications, ...
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CML Output Interfacing The LMH0050 does not include the internal SMPTE cable driver, as its outputs are CML, include internal 50 Ω pull up resistors, and are intended to drive 100 Ω transmission lines. The LMH0050 outputs may either be ...
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FIGURE 8. SMBus Configuration 1 — Host to single device FIGURE 9. SMBus Configuration 2 — Host to multiple devices with SMB_CS signals FIGURE 10. SMBus Configuration 3 — Host to multiple devices with multiple SMBus Interfaces 30017015 11 30017016 ...
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GENERAL PURPOSE I/O PINS GPIO[2:0] The SER has three pins which can be configured to provide direct access to certain register values via a dedicated pin. For example if a particular application required fast action to the condition of the ...
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Application Information PCB RECOMMENDATIONS The SMPTE Serial specifications have very stringent require- ments for output return loss on drivers. The output return loss will be degraded by non-idealities in the connection between the SER (all variants with the exception of ...
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FIGURE 13. Typical SMPTE Application Circuit 14 30017006 ...
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TYPICAL LMH0050 CML APPLICATIONS CIRCUIT A typical application circuit for the LMH0050 is shown in ure 14. The TX interface between the host FPGA and the SER is composed of a 5-bit LVDS Data bus and its LVDS clock. This ...
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FIGURE 14. Typical LMH0050 CML Application Circuit 16 30017013 ...
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SERIAL JITTER OPTIMIZATION The SER is capable of very low jitter operation, however it is dependent on the TXCLK provided by the host in order to op- erate, and depending on the quality of the TXCLK provided, the SER output ...
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Register Descriptions The following table provides details on the device's configu- ration registers. SER Register Detail Table ADD Name Bits 'h 00 device_identificatio The seven MSBs of this register define the SMBus address for the device – the default value ...
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ADD Name Bits 'h 03 GPIO_1 This register configures GPIO_1. Note, if this pin used as an input, then the output must Configuration be TRI-STATE (bit[0]=’0’) and if used as an output, then the input buffer must ...
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ADD Name Bits 'h 11 DVB_ASI Idle_A When in DVB-ASI mode, idle characters are inserted into the datastream when there is no valid data to transmit. The idle character default is K28.5 but if desired, that can be redefined via ...
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ADD Name Bits 'h 27 Event Disable The SER keeps counts of various types of events. These include FIFO over/underflows, and loss of the input signals or clocks. This register allows the user to mask these errors from being counted. ...
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ADD Name Bits 'h 30 CLK_Delay The three msbs from this register are used to insert a programmable delay into the TXCLK path, if the host FPGA does not provide adequate setup and hold times for the SER, this register ...
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... Connection Diagram FIGURE 16. Connection Diagram for 48L LLP Package Ordering Information NSID Speed LMH0340SQ LMH0340SQX LMH0340SQE LMH0040SQ LMH0040SQX LMH0040SQE LMH0070SQ SD LMH0070SQX LMH0070SQE LMH0050SQ LMH0050SQX LMH0050SQE Cable Driver Units per T&R SMPTE 1,000 2,500 250 SMPTE 1,000 2,500 250 SMPTE 1,000 2,500 ...
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Physical Dimensions www.national.com inches (millimeters) unless otherwise noted 48-Lead LLP Plastic Quad Package NS Package Number SQA48A 24 ...
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Notes 25 www.national.com ...
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