K4T1G164QE-HCF8000 Samsung Semiconductor, K4T1G164QE-HCF8000 Datasheet
K4T1G164QE-HCF8000
Specifications of K4T1G164QE-HCF8000
Related parts for K4T1G164QE-HCF8000
K4T1G164QE-HCF8000 Summary of contents
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... K4T1G044QE K4T1G084QE K4T1G164QE 1Gb E-die DDR2 SDRAM Specification 60FBGA & 84FBGA with Lead-Free & Halogen-Free INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHER- WISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOL- OGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Table of Contents 1.0 Ordering Information ................................................................................................................... 4 2.0 Key Features ................................................................................................................................ 4 3.0 Package Pinout/Mechanical Dimension & Addressing ............................................................ 5 3.1 x4 package pinout (Top View) : 60ball FBGA Package 3.2 x8 package pinout (Top View) : 60ball FBGA Package 3.3 x16 package pinout (Top View) : 84ball FBGA Package 3 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Revision History Revision Month Year 1.0 August 2008 1.01 September 2008 1.1 December 2008 - Initial Release - Typo Correction - Updated AC/DC operating condition with the JEDEC update(JESD79-2E DDR2 SDRAM History Rev. 1.1 December 2008 ...
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... The 1Gb DDR2 device is available in 60ball FBGA(x4/x8) and in 84ball FBGA(x16). 85°C, Note : The functionality described and the timing specifications included in CASE this data sheet are for the DLL Enabled mode of operation DDR2 SDRAM DDR2-667 5-5-5 Package K4T1G044QE-HC(L)E6 60 FBGA K4T1G084QE-HC(L)E6 60 FBGA K4T1G164QE-HC(L)E6 84 FBGA DDR2-667 5-5-5 Units 5 tCK DDQ ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 3.0 Package Pinout/Mechanical Dimension & Addressing 3.1 x4 package pinout (Top View) : 60ball FBGA Package DDQ DDL F G BA2 Note : V and V are power and ground for the DLL recommended that they be isolated on the device from V DDL SSDL , V , and SSQ ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 3.2 x8 package pinout (Top View) : 60ball FBGA Package DQ6 V C DDQ D DQ4 V E DDL F G BA2 Note : 1. Pins B3 and A2 have identical capacitances as pins B7 and A8. 2. For a Read, when enabled, strobe pair RDQS & RDQS are identical in function and timing to strobe pair DQS & DQS and input data masking function is disabled ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 3.3 x16 package pinout (Top View) : 84ball FBGA Package DQ14 V C DDQ D DQ12 DQ6 V G DDQ H DQ4 V J DDL K L BA2 Note : V and V are power and ground for the DLL recommended that they be isolated on the device from V DDL ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 3.4 FBGA Package Dimension (x4/x8) (Datum A) (Datum B) 60-∅0.45 Solder ball (Post reflow 0.50 ± 0.05) 0 7.50 ± 0.10 0. 3.20 0.80 1. (0.95) MOLDING AREA (1.90) 7.50 ± 0.10 # DDR2 SDRAM INDEX MARK B 0.35±0.05 1.10±0.10 Rev. 1.1 December 2008 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE (Datum A) (Datum B) 84-∅0.45 Solder ball (Post reflow 0.50 ± 0.05) 0 3.5 FBGA Package Dimension (x16) 7.50 ± 0.10 0. 3.20 0.80 1. (0.95) MOLDING AREA (1.90) 7.50 ± 0.10 # DDR2 SDRAM INDEX MARK B 0.35±0.05 1.10±0.10 Rev. 1.1 December 2008 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 4.0 Input/Output Functional Description Symbol Type Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on the crossing of the CK, CK Input positive edge of CK and negative edge of CK. Output (read) data is referenced to the crossings of CK and CK (both directions of crossing) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 5.0 DDR2 SDRAM Addressing 1Gb Addressing Configuration # of Bank Bank Address Auto precharge Row Address Column Address * Reference information: The following tables are address mapping information for other densities. 256Mb Configuration # of Bank Bank Address Auto precharge Row Address Column Address ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 6.0 Absolute Maximum DC Ratings Symbol Parameter Voltage on V pin relative Voltage on V pin relative DDQ DDQ Voltage on V pin relative DDL DDL Voltage on any pin relative IN, OUT T Storage Temperature STG Note : 1. Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 7.2 Operating Temperature Condition Symbol T Operating Temperature OPER 1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions, please refer to JESD51.2 standard °C operation temperature range, doubling refresh commands in frequency to a 32ms period ( tREFI=3 required, and to enter to self refresh mode at this temperature range, an EMRS command is required to change internal refresh rate ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 7.6 Differential input AC logic Level Symbol Parameter V (AC) AC differential input voltage ID V (AC) AC differential cross point voltage IX Note : 1. V (AC) specifies the input differential voltage |V ID and V is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 9.0 OCD default characteristics Description Output impedance Output impedance step size for OCD calibration Pull-up and pull-down mismatch Output slew rate Note : 1. Absolute Specifications (0°C ≤ T ≤ +95°C; V CASE 2. Impedance measurement condition for output source DC current: V values of V between V ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 10.0 IDD Specification Parameters and Test Conditions (IDD values are for full operating range of Voltage and Temperature, Notes Symbol Operating one bank active-precharge current; IDD0 tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRASmin(IDD); CKE is HIGH HIGH between valid commands; Address bus inputs are SWITCHING; Data bus inputs are SWITCHING Operating one bank active-read-precharge current ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Note : 1. IDD specifications are tested after the device is properly initialized 2. Input slew rate is specified by AC Parametric Test Condition 3. IDD parameters are specified with ODT disabled. 4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11 ...
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... IDD5 115 IDD6 10 IDD7 200 128Mx4 (K4T1G044QE) 800@CL=6 LE7 CF7 LF7 120 165 128Mx8 (K4T1G084QE) 800@CL=6 LE7 CF7 LF7 CE6 120 170 64Mx16 (K4T1G164QE) 800@CL=6 LE7 CF7 LF7 CE6 125 115 200 DDR2 SDRAM Unit 667@CL=5 CE6 LE6 115 mA 10 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 12.0 Input/Output capacitance Parameter Input capacitance, CK and CK Input capacitance delta, CK and CK Input capacitance, all other input-only pins Input capacitance delta, all other input-only pins Input/output capacitance, DQ, DM, DQS, DQS Input/output capacitance delta, DQ, DM, DQS, DQS 13.0 Electrical Characteristics & AC Timing for DDR2-800/667 (0 ° ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 13.3 Timing Parameters by Speed Grade (For information related to the entries in this table, refer to both the general notes and the specific notes following this table.) Parameter DQ output access time from CK/CK DQS output access time from CK/CK Average clock HIGH pulse width ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Parameter Four Activate Window for 1KB page size products Four Activate Window for 2KB page size products CAS to CAS command delay Write recovery time Auto precharge write recovery + precharge time Internal write to read command delay Internal read to precharge command delay ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 14.0 General notes, which may apply for all AC parameters 1. DDR2 SDRAM AC timing reference load Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise repre sentation of the typical system environment or a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 4. Differential data strobe DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit; timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen- dent ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 15.0 Specific Notes for dedicated AC parameters 1. User can choose which active power down exit timing to use via MRS (bit 12). tXARD is expected to be used for fast active power down exit timing. tXARDS is expected to be used for slow active power down exit timing. ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Table 3 - DDR2-400/533 tDS1/tDH1 derating with single-ended data strobe ∆tDS1, ∆tDH1 Derating Values for DDR2-400, DDR2-533(All units in ‘ps’; the note applies to the entire table) 2.0 V/ns 1.5 V/ns ∆tDS ∆tDH ∆tDS ∆tDH 2.0 188 188 167 146 1.5 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal Figure 5 - IIIustration of nominal slew rate for tDS (differential DQS,DQS) tDH tDS REF region nominal slew rate tVAC ∆TF ∆TR V (DC (AC)max Setup Slew Rate ...
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... K4T1G044QE K4T1G084QE K4T1G164QE V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal Note : DQS signal must be monotonic between V Figure 6 - IIIustration of nominal slew rate for tDS (single-ended DQS) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal Figure 7 - IIIustration of tangent line for tDS (differential DQS, DQS) tDS tDH nominal line REF region tangent line ∆TR tangent line[V ...
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... K4T1G044QE K4T1G084QE K4T1G164QE V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal Note : DQS signal must be monotonic between V Figure 8 - IIIustration of tangent line for tDS (single-ended DQS) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal Figure 9 - IIIustration of nominal slew rate for tDH (differential DQS, DQS) tDH tDS REF region nominal REF slew rate region ∆TR V (DC (DC)max ...
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... K4T1G044QE K4T1G084QE K4T1G164QE V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal Note : DQS signal must be monotonic between V Figure 10 - IIIustration of nominal slew rate for tDH (single-ended DQS) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DQS DQS V DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate tangent line [ V Rising Signal Figure 11 - IIIustration of tangent line for tDH (differential DQS, DQS) tDH tDS REF region tangent line REF region nominal line ∆TR ...
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... K4T1G044QE K4T1G084QE K4T1G164QE V DDQ V (AC)min DQS IH V (DC)min IH Note1 V (DC) REF V (DC)max IL V (AC)max DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal Note : DQS signal must be monotonic between V Figure 12 - IIIustration of tangent line for tDH (single-ended DQS) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 9. tIS and tIH (input setup and hold) derating Table 4 - Derating values for DDR2-400, DDR2-533 2.0 V/ns ∆tIS 4.0 +187 3.5 +179 3.0 +167 2.5 +150 2.0 +125 1.5 +83 1.0 0 0.9 -11 Command/ 0.8 -25 Address Slew 0.7 -43 rate(V/ns) 0.6 -67 0.5 -110 0 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Table 5 - Derating values for DDR2-667, DDR2-800 2.0 V/ns ∆tIS 4.0 +150 3.5 +143 3.0 +133 2.5 +120 2.0 +100 1.5 +67 1.0 0 0.9 -5 Command/ 0.8 -13 Address Slew 0.7 -22 rate(V/ns) 0.6 -34 0.5 -60 0.4 -100 0.3 -168 0.25 -200 0.2 -325 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Setup Slew Rate Falling Signal Figure 13 - IIIustration of nominal slew rate for tIS tIH tIS REF region nominal slew rate ∆TF ∆TR V (DC (AC)max Setup Slew Rate REF IL = Rising Signal ∆ ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max IL nominal line V SS Setup Slew Rate Falling Signal Figure 14 - IIIustration of tangent line for tIS tIH tIS nominal line REF region tangent line ∆TR tangent line[V Setup Slew Rate = Rising Signal ∆ ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal tIH tIS REF region nominal REF slew rate region ∆TR V (DC (DC)max REF IL Hold Slew Rate = ∆TR Falling Signal Figure 15 - IIIustration of nominal slew rate for tIH ...
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... K4T1G044QE K4T1G084QE K4T1G164QE DDQ V (AC)min IH V (DC)min IH V (DC) REF V (DC)max IL V (AC)max Hold Slew Rate Rising Signal tIH tIS REF region tangent line REF region nominal line ∆TR tangent line [ V (DC (DC)max ] REF IL = ∆TR tangent line [ V Hold Slew Rate = Falling Signal ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 11. MIN ( tCL, tCH) refers to the smaller of the actual clock LOW time and the actual clock HIGH time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 20. Input waveform timing tDS with differential data strobe enabled MR[bit10]=0, is referenced from the input signal crossing at the V data strobe crosspoint for a rising signal, and from the input signal crossing at the V to the device under test. DQS, DQS signals must be monotonic between V 21 ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 24. tWTR is at lease two clocks (2 x tCK nCK) independent of operation frequency. 25. Input waveform timing with single-ended data strobe enabled MR[bit10 referenced from the input signal crossing at the V single-ended data strobe crossing V IH/L the single-ended data strobe crossing V be monotonic between V ...
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... K4T1G044QE K4T1G084QE K4T1G164QE Definitions : - tCK(avg) tCK(avg) is calculated as the average clock period across any consecutive 200 cycle window. N ∑ tCK(avg) = tCK 200 where - tCH(avg) and tCL(avg) tCH(avg) is defined as the average HIGH pulse width, as calculated across any consecutive 200 HIGH pulses. N ∑ tCH(avg) = ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 36. These parameters are specified per their average values, however it is understood that the following relationship between the average timing and the absolute instantaneous timing holds at all times. (Min and max of SPEC values are to be used for calculations in the table below.) ...
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... K4T1G044QE K4T1G084QE K4T1G164QE 44. For tAOFD of DDR2-400/533, the 1/2 clock of tCK in the 2.5 x tCK assumes a tCH, input clock HIGH pulse width of 0.5 relative to tCK. tAOF,min and tAOF,max should each be derated by the same amount as the actual amount of tCH offset present at the DRAM input with respect to 0.5. ...