K4T1G164QE-HCF8000 Samsung Semiconductor, K4T1G164QE-HCF8000 Datasheet - Page 23

• Manufacturer Part Number: K4T1G164QE-HCF8000
• Manufacturer: Samsung Semiconductor
• Type: DDR2 SDRAMr

Specifications of K4T1G164QE-HCF8000

• Organization: 64Mx16
• Density: 1Gb
• Address Bus: 16b
• Operating Supply Voltage (typ): 1.8V
• Package Type: FBGA
• Operating Temp Range: 0C to 95C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Pin Count: 84
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Compliant

K4T1G084QE
K4T1G164QE
K4T1G044QE
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the setting of the EMRS "Enable DQS" mode bit;
timing advantages of differential mode are realized in system design. The method by which the DDR2 SDRAM pin timings are measured is mode depen-
dent. In single ended mode, timing relationships are measured relative to the rising or falling edges of DQS crossing at V
timing relationships are measured relative to the crosspoint of DQS and its complement, DQS. This distinction in timing methods is guaranteed by design
and characterization. Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must be tied externally to V
through a 20 Ω to 10 kΩ resistor to insure proper operation.
5. AC timings are for linear signal transitions. See Specific Notes on derating for other signal transitions.
6. All voltages are referenced to V
7. These parameters guarantee device behavior, but they are not necessarily tested on each device.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related
They may be guaranteed by device design or tester correlation.
specifications and device operation are guaranteed for the full voltage range specified.
DQS
DQS
DQ
DM
CK/CK
DQS/DQS
DQ
SS
CK
.
CK
DQS
DQS
tCH
Figure 3 - Data Input (Write) Timing
tRPRE
Figure 4 - Data Output (Read) Timing
tWPRE
DQS
DQS
tDQSQ(max)
tCL
V
V
IH
IL
(AC)
(AC)
tDS
DMin
D
23 of 45
tDQSH
tQH
Q
V
V
IH
IL
(AC)
(AC)
DMin
tDS
D
tDQSL
Q
DMin
tDQSQ(max)
D
tDH
V
V
IH
IL
(DC)
(DC)
Q
DMin
D
tDH
tQH
tRPST
V
Q
V
tWPST
IH
IL
(DC)
(DC)
Rev. 1.1 December 2008
REF
DDR2 SDRAM
. In differential mode, these
SS