HYB39S256800DTL-7 Infineon Technologies, HYB39S256800DTL-7 Datasheet - Page 14

• Manufacturer Part Number: HYB39S256800DTL-7
• Manufacturer: Infineon Technologies

Specifications of HYB39S256800DTL-7

• Lead Free Status / Rohs Status: Not Compliant

3
3.1
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive
edge of the clock. The following list shows the truth table for the operation commands.
Table 7
Operation
Bank Active
Bank Precharge
Precharge All
Write
Write with
Autoprecharge
Read
Read with
Autoprecharge
Mode Register Set
No Operation
Burst Stop
Device Deselect
Auto Refresh
Self Refresh Entry
Self Refresh Exit
Clock Suspend Entry Active
Power Down Entry
(Precharge or active
standby)
Clock Suspend Exit
Power Down Exit
Data Write/Output
Enable
Data Write/Output
Disable
1) V = Valid, x = Don’t Care, L = Low Level, H = High Level
2) CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
3) This is the state of the banks designated by BA0, BA1 signals.
4) Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
Data Sheet
provided.
clock suspend mode.
Functional Description
Operation Definition
Truth Table: Operation Command
Active
Active
Device State
Idle
Any
Any
Active
Active
Active
Active
Idle
Any
Any
Idle
Idle
Idle (Self Refr.) L
Idle
Active
Any (Power
Down)
Active
Active
3)
3)
3)
3)
3)
4)
CKE
n-1
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
L
H
H
1)2)
CKE
n
X
X
X
X
X
X
X
X
X
X
X
H
L
H
L
L
H
H
X
X
1)2)
14
DQM
1)2)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
L
H
V
X
X
BA0
BA1
V
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
1)2)
HYB39S256[40/80/16]0D[C/T](L)
AP=
A10
V
L
H
L
H
L
H
V
X
X
X
X
X
X
X
X
X
X
X
X
256-MBit Synchronous DRAM
1)2)
Addr.
1)2)
V
X
X
V
V
V
V
V
X
X
X
X
X
X
X
X
X
X
X
X
Functional Description
10072003-13LE-FGQQ
CS
1)2)
L
L
L
L
L
L
L
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
Rev. 1.02, 2004-02
RAS
1)2)
L
L
L
H
H
H
H
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
CAS
1)2)
H
H
H
L
L
L
L
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
L
WE
1)2)
H
L
L
L
L
H
H
L
H
X
H
H
X
X
X
X
H
X
X
L
X
X