K4H561638H-ZIB3 Samsung Semiconductor, K4H561638H-ZIB3 Datasheet

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K4H561638H-ZIB3

Manufacturer Part Number
K4H561638H-ZIB3
Description
Manufacturer
Samsung Semiconductor
Datasheet

Specifications of K4H561638H-ZIB3

Lead Free Status / Rohs Status
Compliant

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K4H561638H-ZIB3
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K4H561638H
256Mb H-die DDR SDRAM Specification
INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS,
AND IS SUBJECT TO CHANGE WITHOUT NOTICE.
NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE,
EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE,
TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL
INFORMATION IN THIS DOCUMENT IS PROVIDED
ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.
1. For updates or additional information about Samsung products, contact your nearest Samsung office.
2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar
applications where Product failure could result in loss of life or personal or physical harm, or any military or
defense application, or any governmental procurement to which special terms or provisions may apply.
* Samsung Electronics reserves the right to change products or specification without notice.
66 TSOP-II & 60 FBGA
Industrial Temp. -40 to 85°C
Industrial
Rev. 1.3 February 2007
DDR SDRAM

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K4H561638H-ZIB3 Summary of contents

Page 1

... K4H561638H 256Mb H-die DDR SDRAM Specification 66 TSOP-II & 60 FBGA Industrial Temp. -40 to 85°C INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS " ...

Page 2

... K4H561638H Table of Contents 1.0 Key Features ...............................................................................................................................4 2.0 Ordering Information ...................................................................................................................4 3.0 Operating Frequencies................................................................................................................4 4.0 Pin Description ............................................................................................................................5 5.0 Package Physical Dimension .....................................................................................................6 6.0 Block Diagram (4Mbit x16 I/O x4 Banks) ...................................................................................7 7.0 Input/Output Function Description ............................................................................................8 8.0 Command Truth Table.................................................................................................................9 9.0 General Description...................................................................................................................10 10.0 Absolute Maximum Rating .....................................................................................................10 11.0 DC Operating Conditions ........................................................................................................10 12.0 DDR SDRAM Spec Items & ...

Page 3

... K4H561638H Revision History Revision Month Year 1.0 May 2006 1.1 September 2006 1.2 January 2007 1.3 February 2007 - First release - Added DDR400 speed bin - Revised overshoot/undershoot specification following JEDEC SPEC - Added tPDEX on AC parameter specification -Updated IDD SPEC for DDR400 Industrial ...

Page 4

... Support Industrial Temp (-40 to 85°C) • Maximum burst refresh cycle : 8 • 66pin TSOP II, 60Ball FBGA Pb-Free(RoHS compliant) 2.0 Ordering Information Part No. K4H561638H-UI/PCC K4H561638H-UI/PB3 K4H561638H-UI/PB0 K4H561638H-ZI/PB3 K4H561638H-ZI/PB0 3.0 Operating Frequencies B3(DDR333@CL=2.5) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP package Org. Max Freq. ...

Page 5

... K4H561638H 4.0 Pin Description 16M VSSQ DQ14 DQ12 2 DQ15 VDDQ VSSQ 3 VSS DQ13 DQ11 VDD DQ2 DQ4 8 DQ0 VSSQ VDDQ 9 VDDQ DQ1 DQ3 Note : 1. In case of only DQs out of 16 DQs are used, UDQS and DQ0~7 must be used. Organization 16Mx16 DM is internally loaded to match DQ and DQS identically. ...

Page 6

... K4H561638H 5.0 Package Physical Dimension #66 #1 (1.50) (0.71) NOTE REFERENCE ASS’Y OUT QUALITY Units : Millimeters 8.0 0± 0.10 TOP VIEW #34 #33 22.22±0.10 (10×) 0.65TYP 0.30±0.08 0.65±0.08 (10×) 66pin TSOPII / Package dimension ENCAPSULANT AREA 0.35 ± 0.05 π ...

Page 7

... K4H561638H 6.0 Block Diagram ( 4Mb x 16 I/O x4 Banks ) Bank Select CK, CK ADD LCKE LRAS LCBR CK, CK CKE x16 CK, CK Data Input Register Serial to parallel x32 2Mx32 2Mx32 2Mx32 2Mx32 Column Decoder Latency & Burst Length Programming Register LWE LCAS LWCBR Timing Register ...

Page 8

... K4H561638H 7.0 Input/Output Function Description SYMBOL TYPE CK, CK Input CKE Input CS Input RAS, CAS, WE Input LDM,(UDM) Input BA0, BA1 Input 12] Input DQ I/O LDQS,(U)DQS I VDDQ Supply VSSQ Supply VDD Supply VSS Supply VREF Input Clock : CK and CK are differential clock inputs. All address and control input signals are sam- pled on the positive edge of CK and negative edge of CK ...

Page 9

... K4H561638H 8.0 Command Truth Table COMMAND Register Extended MRS Register Mode Register Set Auto Refresh Entry Refresh Self Refresh Exit Bank Active & Row Addr. Read & Auto Precharge Disable Column Address Auto Precharge Enable Write & Auto Precharge Disable Column Address ...

Page 10

... Banks Double Data Rate SDRAM 9.0 General Description The K4H561638H is 268,435,456 bits of double data rate synchronous DRAM organized as 4x 4,194,304 words by 16bits, fabricated with SAMSUNG′s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 333Mb/s per pin ...

Page 11

... K4H561638H 12.0 DDR SDRAM Spec Items & Test Conditions Operating current - One bank Active-Precharge; tRC=tRCmin; tCK=10ns for DDR200, tCK=7.5ns for DDR266, 6ns for DDR333, 5ns for DDR400; DQ,DM and DQS inputs changing once per clock cycle; address and control inputs changing once every two clock cycles. ...

Page 12

... K4H561638H 14.0 Detailed test condition for DDR SDRAM IDD1 & IDD7A IDD1 : Operating current: One bank operation 1. Typical Case: For DDR200,266,333: Vdd = 2.5V, T=25°C; For DDR400: Vdd=2.6V,T=25°C Worst Case : Vdd = 2.7V, T= 10°C 2. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once per clock cycle ...

Page 13

... K4H561638H 15.0 DDR SDRAM IDD spec table Symbol CC(DDR400@CL=3.0) IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 Normal IDD6 Low power IDD7A 16Mx16 (K4H561638H) B3(DDR333@CL=2.5) 110 90 150 125 180 160 180 160 200 180 3 3 1.9 1.9 350 330 ...

Page 14

... K4H561638H 16.0 AC Operating Conditions Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and /CK inputs Input Crossing Point Voltage, CK and /CK inputs Note : 1. VID is the magnitude of the difference between the input level on CK and the input level on /CK. ...

Page 15

... K4H561638H 18.0 Overshoot/Undershoot specification for Data, Strobe and Mask Pins Parameter Maximum peak amplitude allowed for overshoot Maximum peak amplitude allowed for undershoot The area between the overshoot signal and VDD must be less than or equal to The area between the undershoot signal and GND must be less than or equal to ...

Page 16

... K4H561638H 19.0 AC Timming Parameters & Specifications Parameter Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.0 Clock cycle time CL=2.5 CL=3 ...

Page 17

... K4H561638H 20.0 System Characteristics for DDR SDRAM The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM AC CHARACTERISTICS ...

Page 18

... K4H561638H 21.0 Component Notes 1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester ...

Page 19

... K4H561638H Component Notes 17. For CK & CK slew rate ≥ 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH) ...

Page 20

... K4H561638H 22.0 System Notes a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2. Output Figure 2 : Pullup slew rate test load b. Pulldown slew rate is measured under the test conditions shown in Figure 3. Output Figure 3 : Pulldown slew rate test load c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) ...

Page 21

... K4H561638H 23.0 IBIS : I/V Characteristics for Input and Output Buffers DDR SDRAM Output Driver V-I Characteristics DDR SDRAM Output driver characteristics are defined for full and half strength operation as selected by the EMRS bit A1. Figures 3 and 4 show the driver characteristics graphically, and tables 8 and 9 show the same data in tabular format suitable for input into simulation tools ...

Page 22

... K4H561638H Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 6.0 6.8 0.2 12.2 13.5 0.3 18.1 20.1 0.4 24.1 26.6 0.5 29.8 33.0 0.6 34.6 39.1 0.7 39.4 44.2 0.8 43.7 49.8 0.9 47.5 55.2 1.0 51.3 60.3 1.1 54.1 65.2 1 ...

Page 23

... K4H561638H 0.0 Pullup Characteristics for Weak Output Driver 0.0 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 Pulldown Characteristics for Weak Output Driver Figure 4. I/V characteristics for input/output buffers:Pull up(above) and pull down(below) 1.0 2.0 1.0 2.0 Industrial DDR SDRAM Maximum Typical High Typical Low ...

Page 24

... K4H561638H Pulldown Current (mA) Typical Typical Voltage (V) Low High 0.1 3.4 3.8 0.2 6.9 7.6 0.3 10.3 11.4 0.4 13.6 15.1 0.5 16.9 18.7 0.6 19.6 22.1 0.7 22.3 25.0 0.8 24.7 28.2 0.9 26.9 31.3 1.0 29.0 34.1 1.1 30.6 36.9 1 ...

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