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K4H561638H-ZIB3
K4H561638H-ZIB3 | |
|---|---|
| Manufacturer Part Number | K4H561638H-ZIB3 |
| Manufacturer | Samsung Semiconductor |
| K4H561638H-ZIB3 datasheets |
|
Availability: In stock
International delivery:
Warranty: 60 days
×
- We provide standard 60-days warranty for all parts. If warranty differs we always mention it beforehand. In case of return we cover shipping costs.
- If you still have any questions - please contact us
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Shipping terms
- Standard delivery time differs from 5-8 business days if the supplier is a local one to 12-14 days if the suplier is from overseas. If delivery time differs it's always mentioned in our quotation.
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Payment terms
- For new client payment term is payment in advance. At this moment we accept 3 payment methods: wire transfer, PayPal and Western Union. Credit card payment is under constrution and will be introduced soon. Escrow service is acceptable. Net terms for regular customers is not a problem. Working with us is totally safe for you.
- If you still have any questions - please contact us
Specifications of K4H561638H-ZIB3 | |||
|---|---|---|---|
| Lead Free Status / Rohs Status | Compliant | ||
PrevNext
K4H561638H
1.0 Key Features
• VDD : 2.5V ± 0.2V, VDDQ : 2.5V ± 0.2V for DDR266, 333
• VDD : 2.6V ± 0.1V, VDDQ : 2.6V ± 0.1V for DDR400
• Double-data-rate architecture; two data transfers per clock cycle
• Bidirectional data strobe [L(U)DQS] (x16)
• Four banks operation
• Differential clock inputs(CK and CK)
• DLL aligns DQ and DQS transition with CK transition
• MRS cycle with address key programs
-. Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
• All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
• Data I/O transactions on both edges of data strobe
• Edge aligned data output, center aligned data input
• LDM,UDM for write masking only (x16)
• Auto & Self refresh
• 7.8us refresh interval(8K/64ms refresh)
•
Support Industrial Temp (-40 to 85°C)
• Maximum burst refresh cycle : 8
• 66pin TSOP II, 60Ball FBGA
Pb-Free(RoHS compliant)
2.0 Ordering Information
Part No.
K4H561638H-UI/PCC
K4H561638H-UI/PB3
K4H561638H-UI/PB0
K4H561638H-ZI/PB3
K4H561638H-ZI/PB0
3.0 Operating Frequencies
B3(DDR333@CL=2.5)
Speed @CL2
Speed @CL2.5
Speed @CL3
CL-tRCD-tRP
package
Org.
Max Freq.
CC(DDR400@CL=3.0)
16M x 16
B3(DDR333@CL=2.5)
B0(DDR266@CL=2.5)
B3(DDR333@CL=2.5)
16M x 16
B0(DDR266@CL=2.5)
A2(DDR266@CL=2.0)
133MHz
166MHz
-
2.5-3-3
Industrial
DDR SDRAM
Interface
SSTL2
66pin TSOP II
SSTL2
B0(DDR266@CL=2.5)
133MHz
100MHz
133MHz
133MHz
-
2-3-3
2.5-3-3
Rev. 1.3 February 2007
Package
60 FBGA
-
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