MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet
MT45W1ML16PAFA-70 WT
Specifications of MT45W1ML16PAFA-70 WT
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MT45W1ML16PAFA-70 WT Summary of contents
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... Standby Power W Standard Low-Power (32Mb) L • Operating Temperature Range 1 V Wireless (-25°C to +85°C) W Industrial (-40°C to +85° Note 1: Contact factory. 1 -60 -70 -85 1 ADVANCE 2 MEG x 16, 1 MEG x 16 MT45W1MW16PAFA MT45W1ML16PAFA Figure 1: 48-Ball FBGA LB# OE ZZ# A4 DQ8 UB# A3 CE# DQ0 A6 DQ9 DQ10 ...
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General Description Micron CellularRAM products are high-speed, CMOS dynamic random access memories that have been developed for low-power portable applications. The MT45W2Mx16PA is a 32Mb device organized as 2 Meg x 16 bits, and the MT45W1Mx16PA is a 16Mb ...
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Table 1: FBGA Ball Descriptions FBGA BALL ASSIGNMENT SYMBOL TYPE A3, A4, A5, B3, A[20:0] Input B4, C3, C4, D4, H2, H3, H4, H5, G3, G4, F3, F4, E4, D3, H1, G2 ZZ# Input B5 CE# Input A2 ...
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... Table 3: Abbreviated Component Marks— CellularRAM FBGA-Packaged Components PART NUMBER MT45W2MW16PAFA-85 WT MT45W2MW16PAFA-70 WT MT45W2ML16PAFA-85 WT MT45W2ML16PAFA-70 WT MT45W1MW16PAFA-85 WT MT45W1MW16PAFA-70 WT MT45W1ML16PAFA-85 WT MT45W1ML16PAFA-70 WT 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ASYNC/PAGE CellularRAM MEMORY ENGINEERING SAMPLE PX400 PX401 PX403 PX404 PX104 PX105 PX107 PX108 Micron Technology, Inc., reserves the right to change products or specifications without notice. ...
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Functional Description In general, the MT45W2Mx16PA device and the MT45W1Mx16PA device are high-density alternatives to SRAM and Pseudo SRAM products, popular in low- power, portable applications. The MT45W2Mx16PA contains 33,554,432 bits organized as 2,097,152 addresses by 16 bits.The MT45W1Mx16PA contains ...
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Page Mode READ Operation Page mode is a performance-enhancing extension to the legacy asynchronous READ operation. In page- mode-capable products, an initial asynchronous read access is performed, then adjacent addresses can be quickly read by simply changing the low-order address. ...
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CR[4] to “1” using this method. However, using software access to write to the CR alters the function of the ZZ# pin so that ZZ# LOW no longer initiates PAR, although ZZ# continues to enable WRITEs to ...
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Configuration Register Operation The configuration register (CR) defines how the Cel- lularRAM device performs its transparent self refresh. Altering the refresh parameters can dramatically reduce current consumption during standby mode. Page mode control is also embedded into the CR. This ...
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Figure 9: Software Access Load Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA Figure 10: Software Access Read Configuration Register ADDRESS CE# OE# WE# LB#/UB# DATA NOTE: CE# must be HIGH for 150ns before performing the cycle that reads the ...
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Partial Array Refresh (CR[2:0]) Default = Full Array Refresh The PAR bits restrict refresh operation to a portion of the total memory array. This feature allows the sys- tem to reduce current by only refreshing that part of the memory ...
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Table 4: Configuration Register Bit Mapping A[20:8] 20– 8 RESERVED All must be set to "0" CR[7] Page Mode Enable/Disable 0 Page Mode Disabled (default) 1 Page Mode Enabled CR[6] CR[5] Maximum Case Temp +85˚ Internal ...
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Absolute Maximum Ratings* Voltage to Any Ball Except Relative ...
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Table 8: Temperature Compensated Refresh Specifications and Conditions DESCRIPTION CONDITIONS Temperature Compensated Refresh Standby Current NOTE: I (MAX) values measured with FULL ARRAY refresh. TCR Table 9: Partial Array Refresh Specifications and ...
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Table 11: Capacitance Specifications and Conditions DESCRIPTION Input Capacitance Input/Output Capacitance (DQ) NOTE: 1. These parameters are verified in device characterization and are not 100% tested. Figure 11: AC Input/Output Reference Waveform Input V SS NOTE: ...
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Table 13: READ Cycle Timing Requirements PARAMETER Address Access Time Page Access Time LB#/UB# Access Time LB#/UB# Disable to High-Z Output LB#/UB# Enable to Low-Z Output Chip Select Access Time Chip Disable to High-Z Output Chip Enable to Low-Z Output ...
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Table 15: Load Configuration Register Timing Requirements DESCRIPTION Address Setup Time Address Valid to End of Write Chip Deselect to ZZ# LOW Chip Enable to End of Write Write Cycle Time Write Pulse Width Write Recovery Time ZZ# LOW to ...
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Figure 14: Load Configuration Register ADDRESS LB#/UB# Table 18: Load Configuration Register Timing Requirements -70 SYMBOL MIN MAX MIN CDZZ 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN ASYNC/PAGE CellularRAM ...
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Figure 15: Deep Power-Down—Entry/Exit t CDZZ t ZZ (MIN) ZZ# CE# Table 19: Deep Power-Down Timing Parameters SYMBOL t CDZZ (MIN) 09005aef80d481d3 AsyncCellularRAM_16_32.fm - Rev. A 2/18/ MEG x 16, 1 MEG x 16 ...
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Figure 16: Single READ Operation (WE ADDRESS LB#/UB# DATA-OUT Table 20: READ Timing Parameters -70 SYMBOL MIN MAX MIN BHZ t 10 BLZ 09005aef80d481d3 ...
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Figure 17: Page Mode READ Operation (WE ADDRESS A[20:4] ADDRESS A[3:0] CE# LB#/UB# OE# DATA-OUT Table 21: Page Mode READ Timing Parameters -70 SYMBOL MIN MAX MIN APA ...
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Figure 18: WRITE Cycle (WE# Control) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 22: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEM ...
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Figure 19: WRITE Cycle (CE# Control) ADDRESS LB#/UB# DATA-IN DATA-OUT Table 23: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEH 10 t CEM ...
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Figure 20: WRITE Cycle (LB#/UB# Control) ADDRESS CE# LB#/UB# WE# OE# DATA-IN DATA-OUT Table 24: WRITE Timing Parameters -70 SYMBOL MIN MAX MIN CEM ...
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SEATING PLANE C 0.10 C 48X Ø0.35 SOLDER BALL DIAMETER REFERS TO POST REFLOW CONDITION. THE PRE-REFLOW DIAMETER IS Ø0.35. BALL A6 5.25 2.625 ±0.05 1.875 ±0.050 NOTE: 1. All dimensions in millimeters, MAX/MIN or typical where noted. ...
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APPENDIX A How Extended Timings Impact TM CellularRAM Operation Introduction CellularRAM products use a DRAM technology that periodically requires refresh to ensure against data corruption. CellularRAM devices include on-chip circuitry that performs the required refresh in a man- ner that ...
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Page Mode READ Operation When a CellularRAM device is configured for page mode operation, the address inputs are used to accel- erate read accesses and cannot be used by the on-chip circuitry to schedule refresh. If CE# is LOW longer ...
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Revision History Rev. A, Advance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...