MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 2

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

General Description
CMOS dynamic random access memories that have
been developed for low-power portable applications.
The MT45W2Mx16PA is a 32Mb device organized as 2
Meg x 16 bits, and the MT45W1Mx16PA is a 16Mb
device organized as 1 Meg x 16 bits. These devices
include the industry-standard, asynchronous memory
interface found on other low-power SRAM or Pseudo
SRAM offerings.
minimize power consumption. The core voltage has
been reduced to a 1.80V operating level. To maintain
compatibility with different memory bus interfaces,
CellularRAM devices are available with I/O voltages of
3.00V, 2.50V or 1.80V.
how the CellularRAM device performs on-chip refresh
and whether page mode read accesses are permitted.
This register is automatically loaded with a default set-
ting during power-up and can be updated at any time
during normal operation.
NOTE:
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
Micron
Operating voltages have been reduced in an effort to
A user-accessible configuration register (CR) defines
Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing
diagrams for detailed information.

CellularRAM products are high-speed,
WE#
OE#
UB#
CE#
LB#
ZZ#
(for 32Mb)
(for 16Mb)
A[20:0]
A[19:0]
Control
Logic
Figure 2: Functional Block Diagram
2 Meg x 16 and 1 Meg x 16
Address Decode
Configuration
Register (CR)
Logic
ASYNC/PAGE CellularRAM MEMORY
2
bus, CellularRAM products incorporate a transparent
self refresh mechanism. The hidden refresh requires
no additional support from the system memory con-
troller and has no significant impact on device read/
write performance.
sumption during self refresh. CellularRAM products
include three system-accessible mechanisms to mini-
mize refresh current. Temperature compensated
refresh (TCR) uses an on-chip sensor to adjust the
refresh rate to match the device temperature. The
refresh rate decreases at lower temperatures to mini-
mize current consumption during standby. TCR can
also be set by the system for maximum device temper-
atures of +85°C, +45°C, and +15°C. Setting the sleep
enable pin ZZ# to LOW enables one of two low-power
modes: partial array refresh (PAR); or deep power-
down (DPD). PAR limits refresh to only that part of the
DRAM array that contains essential data. DPD halts
refresh operation altogether and is used when no vital
information is stored in the device. These three refresh
mechanisms are accessed through the CR.
To operate seamlessly on an asynchronous memory
Special attention has been focused on current con-
(1,024K x 16)
2,048K x 16
MEMORY
Micron Technology, Inc., reserves the right to change products or specifications without notice.
ARRAY
DRAM
2 MEG x 16, 1 MEG x 16
Output
Buffers
Input/
MUX
and
©2004 Micron Technology, Inc. All Rights Reserved.
DQ[7:0]
DQ[15:8]
ADVANCE