MT45W1ML16PAFA-70 WT Micron Technology Inc, MT45W1ML16PAFA-70 WT Datasheet - Page 3

• Manufacturer Part Number: MT45W1ML16PAFA-70 WT
• Manufacturer: Micron Technology Inc

Specifications of MT45W1ML16PAFA-70 WT

• Operating Temperature (max): 85C
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant

Table 1:
Table 2:
NOTE:
09005aef80d481d3
AsyncCellularRAM_16_32.fm - Rev. A 2/18/04 EN
1. When LB# and UB# are in select mode (LOW), DQ[15:0] are affected. When LB# only is in select mode, only DQ[7:0]
2. When the device is in standby mode, control inputs (WE#, OE#), address inputs, and data inputs/outputs are inter-
3. When WE# is invoked, the OE# input is internally disabled and has no effect on the I/Os.
4. The device will consume active power in this mode whenever addresses are changed.
5. V
6. DPD is enabled when configuration register bit CR[4] is “0”; otherwise, PAR is enabled.
FBGA BALL
ASSIGNMENT
MODE
Standby
Read
Write
No Operation
PAR
DPD
Load
Configuration
Register
H2, H3, H4, H5,
A3, A4, A5, B3,
E4, D3, H1, G2,
B4, C3, C4, D4,
B6, C5, C6, D5,
B1, C1, C2, D2,
G3, G4, F3, F4,
E5, F5, F6, G6,
E2, F2, F1, G1
are affected. When UB# only is in the select mode, DQ[15:8] are affected.
nally isolated from any external influence.
IN
= V
H6
A6
B5
A2
G5
A1
B2
D6
D1
E3
E1
E6
CC
Q or 0V; all device balls must be static (unswitched) in order to achieve minimum standby current.
FBGA Ball Descriptions
Bus Operations
SYMBOL
Partial Array Refresh
DQ[15:0]
A[20:0]
Deep Power-Down
V
V
WE#
OE#
UB#
ZZ#
CE#
LB#
V
V
NC
CC
SS
CC
SS
Q
Q
Standby
POWER
Active
Active
Active
Idle
Output
Supply
Supply
Supply
Supply
Input/
Input
TYPE
Input
Input
Input
Input
Input
Input
—
Address Inputs: Inputs for the address accessed during READ or WRITE operations.
The address lines are also used to define the value to be loaded into the CR. On
the 16Mb device, A20 (ball H6) is not internally connected.
Sleep Enable: When ZZ# is LOW, the CR can be loaded or the device can enter one
of two low-power modes (DPD or PAR).
Chip Enable: Activates the device when LOW. When CE# is HIGH, the device is
disabled and goes into standby power mode.
Output Enable: Enables the output buffers when LOW. When OE# is HIGH, the
output buffers are disabled.
Write Enable: Enables WRITE operations when LOW.
Lower Byte Enable. DQ[7:0]
Upper Byte Enable. DQ[15:8]
Data Inputs/Outputs.
Not internally connected.
Device Power Supply: (1.7V–1.95V) Power supply for device core operation.
I/O Power Supply: (1.8V, 2.5V, 3.0V) Power supply for input/output buffers.
V
V
SS
SS
CE#
Q must be connected to ground.
H
H
H
L
L
L
L
must be connected to ground.
WE#
H
X
X
X
X
L
L
ASYNC/PAGE CellularRAM MEMORY
3
OE#
X
X
X
X
X
X
L
LB#/UB#
Micron Technology, Inc., reserves the right to change products or specifications without notice.
X
X
X
X
X
L
L
DESCRIPTION
2 MEG x 16, 1 MEG x 16
ZZ#
H
H
H
H
L
L
L
©2004 Micron Technology, Inc. All Rights Reserved.
DQ[15:0]
Data-Out
Data-In
High-Z
High-Z
High-Z
High-Z
X
1
ADVANCE
NOTES
1, 3, 4
2, 5
1, 4
4, 5
6
6