DAC121C081CISDX/NOPB National Semiconductor, DAC121C081CISDX/NOPB Datasheet - Page 15

• Manufacturer Part Number: DAC121C081CISDX/NOPB
• Description: DAC 12BIT MICROPWR I2C 6-LLP
• Manufacturer: National Semiconductor
• Series: PowerWise®r

Specifications of DAC121C081CISDX/NOPB

• Settling Time: 6µs
• Number Of Bits: 12
• Data Interface: I²C
• Number Of Converters: 1
• Voltage Supply Source: Single Supply
• Power Dissipation (max): 730µW
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 6-LLP
• For Use With: DAC121C08XEB - BOARD EVAL FOR DAC121C081/5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: DAC121C081CISDX

1.4 SERIAL INTERFACE
The I
modes. Standard mode (100kHz) and Fast mode (400kHz)
are functionally the same and will be referred to as Standard-
Fast mode in this document. High-Speed mode (3.4MHz) is
an extension of Standard-Fast mode and will be referred to
as Hs-mode in this document. The following diagrams de-
scribe the timing relationships of the clock (SCL) and data
(SDA) signals. Pull-up resistors or current sources are re-
quired on the SCL and SDA busses to pull them high when
they are not being driven low. A logic zero is transmitted by
driving the output low. A logic high is transmitted by releasing
the output and allowing it to be pulled-up externally. The ap-
propriate pull-up resistor values will depend upon the total bus
capacitance and operating speed.
1.4.1 Basic I
The I
to operate on the same bus. To facilitate this bus configura-
tion, each device has a unique hardware address which is
referred to as the "slave address." To communicate with a
particular device on the bus, the controller (master) sends the
slave address and listens for a response from the slave. This
response is referred to as an acknowledge bit. If a slave on
the bus is addressed correctly, it Acknowledges (ACKs) the
master by driving the SDA bus low. If the address doesn't
match a device's slave address, it Not-acknowledges
(NACKs) the master by letting SDA be pulled high. ACKs also
occur on the bus when data is being transmitted. When the
1.4.2 Standard-Fast Mode
In Standard-Fast mode, the master generates a start condi-
tion by driving SDA from high to low while SCL is high. The
Start condition is always followed by a 7-bit slave address and
a Read/Write bit. After these eight bits have been transmitted
by the master, SDA is released by the master and the
DAC121C081 either ACKs or NACKs the address. If the slave
address matches, the DAC121C081 ACKs the master. If the
address doesn't match, the DAC121C081 NACKs the master.
For a write operation, the master follows the ACK by sending
the upper eight data bits to the DAC121C081. Then the
DAC121C081 ACKs the transfer by driving SDA low. Next,
the lower eight data bits are sent by the master. The
DAC121C081 then ACKs the transfer. At this point, the DAC
2
2
C interface is bi-directional and allows multiple devices
C-compatible interface operates in all three speed
2
C Protocol
FIGURE 4. Basic Operation.
15
master is writing data, the slave ACKs after every data byte
is successfully received. When the master is reading data, the
master ACKs after every data byte is received to let the slave
know it wants to receive another data byte. When the master
wants to stop reading, it NACKs after the last data byte and
creates a Stop condition on the bus.
All communication on the bus begins with either a Start con-
dition or a Repeated Start condition. The protocol for starting
the bus varies between Standard-Fast mode and Hs-mode.
In Standard-Fast mode, the master generates a Start condi-
tion by driving SDA from high to low while SCL is high. In Hs-
mode, starting the bus is more complicated. Please refer to
section 1.4.3 for the full details of a Hs-mode Start condition.
A Repeated Start is generated to either address a different
device, or switch between read and write modes. The master
generates a Repeated Start condition by driving SDA low
while SCL is high. Following the Repeated Start, the master
sends out the slave address and a read/write bit as shown in
Figure 4. The bus continues to operate in the same speed
mode as before the Repeated Start condition.
All communication on the bus ends with a Stop condition. In
either Standard-Fast mode or Hs-Mode, a Stop condition oc-
curs when SDA is pulled from low to high while SCL is high.
After a Stop condition, the bus remains idle until a master
generates a Start condition.
Please refer to the Phillips I
Jan, 2000) for a detailed description of the serial interface.
output updates to reflect the contents of the 16-bit DAC reg-
ister. Next, the master either sends another pair of data bytes,
generates a Stop condition to end communication, or gener-
ates a Repeated Start condition to communicate with another
device on the bus.
For a read operation, the DAC121C081 sends out the upper
eight data bits of the DAC register. This is followed by an ACK
by the master. Next, the lower eight data bits of the DAC reg-
ister are sent to the master. The master then produces a
NACK by letting SDA be pulled high. The NACK is followed
by a master-generated Stop condition to end communication
on the bus, or a Repeated Start to communicate with another
device on the bus.
2
C
®
Specification (Version 2.1
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