TXC-06312BIOG Transwitch Corporation, TXC-06312BIOG Datasheet
TXC-06312BIOG
Specifications of TXC-06312BIOG
Related parts for TXC-06312BIOG
TXC-06312BIOG Summary of contents
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... Microprocessor APS Port Interface • 3 Enterprise Drive • Shelton, Connecticut 06484 • Fax: 203-926-9453 • www.transwitch.com ® Telecom Bus Interface TXC-06312B DATA SHEET TXC-06312B-MB, Ed. 2 June 2005 DCC Clocks, TERMINAL SIDE Ports Control/Status 77.76 MHz Telecom Bus Boundary Scan • USA ...
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... U.S. and/or foreign patents issued or pending Copyright 2005 TranSwitch Corporation TL3M and VTXP are trademarks of TranSwitch Corporation TranSwitch, TXC, TEMx28, EtherMap and PHAST are registered trademarks of TranSwitch Corporation PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 - IMPORTANT NOTICE - ...
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... Microprocessor Controlled Hardware Reset (RESETH)........................................... 91 10.3.3 Microprocessor Controlled Reset Per Clock Domain ............................................... 91 10.4 Powerup, Initialization and Startup ...................................................................................... 92 10.4.1 Powerup of the CDR/CS........................................................................................... 92 10.5 PRBS Generator and PRBS Analyzer................................................................................. 95 10.6 Line Interface....................................................................................................................... PHAST-12N Device DATA SHEET TXC-06312B T C ABLE OF ONTENTS PRELIMINARY TXC-06312B-MB, Ed. 2 Page June 2005 ...
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... Drop Bus Parity Selection....................................................................................... 131 12.1.2 Drop Bus Delay....................................................................................................... 132 12.1.3 Drop Bus High Impedance...................................................................................... 132 12.2 Add Bus Interface .............................................................................................................. 132 12.2.1 Add Bus Timing Modes........................................................................................... 133 12.2.2 Add Bus Parity Selection ........................................................................................ 133 12.2.3 Add Bus Delay ........................................................................................................ 134 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... They must also contact the Applications Engineering Department to ensure that they are provided with the latest avail- able information about the product, especially before undertaking development of new designs incorporating the product PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Supported SDH/SONET Mapping .................................................................................................................. 13 2. PHAST-12N TXC-06312B Block Diagram ...................................................................................................... 17 3. PHAST-12N Functional Model........................................................................................................................ 18 4. PHAST-12N TXC-06312B 376-Lead Plastic Ball Grid Array Package Lead Diagram.................................... 21 5. DROP Bus Timing .......................................................................................................................................... 54 6. Add Bus Timing (ADD Slave Mode: Timing Signals Are Inputs)..................................................................... 55 7. ADD Bus Timing (ADD Master Mode: Timing Signals Are Outputs)............................................................... 56 8 ...
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... Boundary Scan Schematic ........................................................................................................................... 149 55. PHAST-12N TXC-06312B 376-Lead Plastic Ball Grid Array Package ......................................................... 196 56. STM-4/OC- STM-1/OC-3 Terminal Mux.......................................................................................... 197 57. STM-4/OC- STM-1/OC-3 1+1, 1:1 APS Terminal Mux ................................................................... 197 58. STM-4/OC- STM-1/OC-3 Ethernet and TDM Terminal Mux ........................................................... 198 Table 1. Memory Map Overview................................................................................................................................. 150 2. Global Control (T_GLOBAL_CONTROL) ..................................................................................................... 151 3 ...
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... POH Monitor Defects (T_VCXPM_Defects) ................................................................................................. 192 88. POH Monitor Common Configuration (T_VCXPM_Common_Config).......................................................... 192 89. POH Monitor Status (T_VCXPM_Common_Status)..................................................................................... 194 90. J1 TTI Stable (T_VCXPM_Report) ............................................................................................................... 194 91. POH Monitor Per Path (T_VCXPM_Status) ................................................................................................. 194 92. POH Monitor Path Status (T_VCXPM_POH_Status) ................................................................................... 195 93. POH Monitor Performance Counters (T_VCXPM_PM) ................................................................................ 195 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Changed edition number and date. Changed document status from PRODUCT PREVIEW to PRELIMINARY. 3-7 Updated 9 Added 23 Modified Name/Function column for Symbol Reserved. 25 Modified Name/Function column for Symbol LINETXCAP. 26 Modified Name/Function column for table 45 Modified Conditions for Maximum Ratings and Environmental 47 Added last sentence in Requirements. ...
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... Modified section 135 Added last paragraph in section 153 Modified 180 Modified Description column for Offset 0x0000, Bits 13-0. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Summary of the Change Microprocessor Controlled Reset Per Clock APS Interface. APS Interface Generator APS Port Architecture. Figure 39 and added Figure title ...
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... Telcordia GR-253-CORE SONET Common Generic Criteria, Rev 3, September 2000 Telcordia GR-499-CORE Transport Systems Generic Requirements: Common Requirements, Issue 2, December 1998 TANDARDS OCUMENTATION ® Description PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B -12N device are listed below. June 2005 ...
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... TranSwitch device software deliverables and is meant to be easily integrated with them. The application software calls the driver functions to configure, control and manage the PHAST-12N device. The device driver insulates the application from the internal details of the device register usage and provides a higher level of abstraction. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 O VERVIEW ...
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... AU-4 AUG-1 STS-3c STS-3c SPE x3 VC-3 AU-3 STS-1 STS-1 SPE PHAST-12N Device DATA SHEET TXC-06312B 1.0 F EATURES X=2 STS-6c Payload X=3 STS-9c Payload C-4-4c C-4-Xc X=4 STS-12c STS-3c-Xc Payload Payload C-4 STS-3c Payload C-3 STS-1 Payload PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Block and bit error performance monitoring counters • D4-D12 DCC can be accessible via the DCC port • Insertion and monitoring of remote information (RDI, REI) • Insertion and monitoring of MS/line AIS • Insertion and monitoring of the K1/K2 APS signal PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Features - - ...
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... VC-3/STS-1 SPE granularity allowing cross connecting at VC-3/VC-4/VC-4-Xc/STS-1/ STS-3c/STS-6c/STS-9c/STS-12c SPE level • Path loopbacks and multi-casts are supported • Each individual output channel can be forced to source an AIS or unequipped mainte- nance signal Features - PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B June 2005 ...
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... Interrupt mask bits for controlling generation of hardware interrupt requests 1.10 TESTING • Line loopbacks • High order path loopbacks via the cross connect • Boundary scan 1.11 DEVICE DRIVER • Device configuration • Fault monitoring • Performance monitoring PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Features - - ...
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... Analyzer Generator POH Port POH POH Ring Port Generator Monitor Retimer DROP ADD Telecom Bus Telecom Bus @ 77.76 MHz Figure 2. PHAST-12N TXC-06312B Block Diagram PHAST-12N Device DATA SHEET TXC-06312B D LOCK IAGRAM APS Port @ 622.08 Mbit/s Clock Clock/Data Synthesis Recovery APS Port ...
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... OSn_TT OSn/RSn_A RSn_TT RSn/MSn_A MSn_TT MSn/MSnP_A MSnP_TT MSn/Sn_A Note: Additional information regarding the Functional Model of the PHAST-12N can be found in ITU-T G.783 Standards Documentation. Figure 3. PHAST-12N Functional Model PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Functional Model - - 3.0 F UNCTIONAL APS_TT APS/MSnP_A MSnP_TT Sn_TTm MSn/Sn_A ...
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... APS port. The high order path containers are retimed to the local System Clock. High order POH monitoring is performed on all received high order path containers for SNC/P and UPSR applications Block Diagram Description - 4 LOCK IAGRAM PHAST-12N Device DATA SHEET TXC-06312B D ESCRIPTION PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... REI, can be inserted from the internal or external ring port interface. This selection can be made on a per high order path basis. For Test purposes, a PRBS pattern can be generated and inserted on a particular path by the PHAST-12N. PRBS can be analyzed for bit errors on the receive side. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Block Diagram Description - ...
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... This is the bottom view. The leads are solder balls. See This view is rotated relative to the bottom view in Some signal Symbols have been abbreviated to fit the space available. The Symbols are shown in full in the Figure 4. PHAST-12N TXC-06312B 376-Lead Plastic Ball Grid Array Package Lead Diagram Lead Diagram - 5.0 L ...
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... M10, M11, M12, M13, M14, M9, N10, N11, N12, N13, N14, N9, P10, P11, P12, P13, P14, P9, V18, V5, W19, W4 VSSA18RPA AA16, AB16 VSSA18TPA AA8, AB12 VSSA33LVPCPST AA14, AA15 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - 6.0 L EAD I/O/P Name/Function P Digital Core 1.8V supply: +1.8V +/- PLL / Clock Recovery & ...
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... Can not be used in STM-4/OC-12 mode. I LVPECL Serial SDH/SONET Receive Data #4: 155.52 Mbit/s bit- serial data from electro/optical transceivers. Can not be used in STM-4/OC-12 mode. PHAST-12N Device DATA SHEET TXC-06312B Name/Function Name/Function Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... LINERXCLK1 AA19 LINERXCLK2 AB21 LINERXCLK3 W18 LINERXCLK4 Y19 LINERXCAP Y17 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type I LVTTL Signal Detect #1: Signal from the optical receiver for line #1 indicating signal presence. I LVTTL Signal Detect #2: Signal from the optical receiver for line #2 indicating signal presence ...
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... APS port data stream on APSRXDATAP/N. The clock rate is programmable to be either 19.44 or 77.76 MHz. PHAST-12N Device DATA SHEET TXC-06312B Name/Function STM-1/OC-3 STM-4/OC-12 Application Application N/A N/A 1.0 F 1.0 F Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... I LVTTL Receive Reference Clock: Optional Reference clock for the receive clock and data recovery units. This clock is required for line/loop-time applications, when REFTXCLK1 and REFTXCLK2P/N are not present. The clock rate is programmable to be either 19.44 or 77.76 MHz. The frequency tolerance for this clock is ± 100 ppm ...
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... I LVTTL Transmit Reference Frame Sync: Optional 8 kHz refer- ence frame sync pulse. If present, this input must be syn- chronous to LINETXCLK and shall be at least 1 77.76 MHz clock cycle wide = 12.86 ns. O LVCMOS System Reference Frame Sync: 8 kHz reference frame 8mA sync pulse ...
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... DCCRXCLK1 V1 O DCCRXCLK2 W1 O DCCRXCLK3 T4 O DCCRXCLK4 U3 O PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type Name/Function LVCMOS Receive DCC Data #4: Bit-serial data from the TOH monitor of 4mA receive line interface # external LAPD interface control- ler or similar device. This data can be optionally selected to provide D1-D3 (RS/ Section DCC) or D4-D12 (MS/Line DCC) ...
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... Transmit DCC Clock #4: The DCCTXDATA4 signal is clocked 8mA into the PHAST-12N on negative transitions of this clock. If MS/Line DCC is selected for DCCTXDATA4, the frequency is 576 kHz, if RS/Section DCC is selected for DCCTXDATA4, the frequency is 192 kHz. PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... M21 I/O(T) CBADJ0J1 M22 I/O(T) CBADPAR M20 I CBADCLK L22 I/O(T) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type Name/Function LVTTLp Add Telecom Bus Timing Mode: Selects Master or Slave timing mode on the Add Telecom Bus. If CBADT is high, Slave timing is selected: CBADCLK, CBAD- SPE and CBADJ0J1 are inputs ...
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... LRPRXDATA. O LVCMOS Receive Line Ring Port Data: A serial frame contain- 4mA ing the remote information, REI and RDI, for the individ- ual high order path signals. PHAST-12N Device DATA SHEET TXC-06312B Name/Function Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... PHAST-12N device, it must be tied to VSS. I LVTTL Transmit Line Ring Port Frame Sync: An active high, one LRPTXCLK clock-cycle wide frame sync pulse that identifies the first bit in the data stream present on LRPTXDATA. When this lead is not connected to LRPRXFS of a mate PHAST-12N device, it must be tied to VSS. ...
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... PHAST-12N device, it must be tied to VSS. I LVTTL Transmit HO Ring Port Frame Sync: An active high, one PRPTXCLK clock-cycle wide frame sync pulse that identifies the first bit in the data stream present on PRPTXDATA. When this lead is not connected to LRPRXFS of a mate PHAST-12N device, it must be tied to VSS. ...
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... TOH byte requested on the TOHTXDATA lead. O LVCMOS Transmit TOH Port Data Latch Enable: An active high, 8 8mA TOHTXCLK clock-cycle wide pulse indicating that valid data is present on TOHTXDATA. I LVTTL Transmit TOH Port Data: The value of the TOH byte requested by TOHTXADDR is clocked in as the 8 consec- utive states while TOHTXDLE is high ...
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... POHTXDATA is clocked in on the rising edge of this clock. Its frequency is 77.76 MHz. LVCMOS Transmit HO POH Port Address Latch Enable: An active 8mA high, 8 POHTXCLK clock-cycle wide pulse indicating that a valid address is present on POHTXADDR. LVCMOS Transmit HO POH Port Address: The 8 consecutive states 8mA ...
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... A2 I MPACKLEVEL D5 I Note: The Generic Intel, Generic Motorola, Motorola MPC860 and Motorola MPC8260 Local Bus - Host Processor interfaces are shared on the same leads. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type LVCMOS General Purpose Output #1: Active high output, e.g., to control 4mA the external electro/optical transceiver ...
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... PHAST-12N through a read or write cycle. Intel notation: CS LVTTL Read Strobe (Active low): This active low lead initiates a read transfer between the host processor and the PHAST-12N. Intel notation: RD PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... F3 MPA03 G4 MPA02 D1 MPA01 E1 MPA00 F2 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type LVTTL Write Strobe (Active Low): This active low lead initiates a write transfer between the host processor and the PHAST-12N. Intel notation: WR Ready: For a write access, an active edge on this lead indi- 24mA cates that data is written to the addressed memory location ...
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... Active level depends on MPACKLEVEL. Motorola notation: DSACK O LVCMOS Interrupt Request: This lead signals an interrupt request to 8mA the host processor. Active level depends on MPINTLEVEL. PHAST-12N Device DATA SHEET TXC-06312B Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... J2 MPD03 K3 MPD02 J1 MPD01 K2 MPD00 L4 MPSEL K1 MPTS L3 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type I LVTTL Microprocessor Clock: This lead is the clock sourced by the microprocessor being interfaced to this device. Its max. frequency is 50 MHz. Motorola MPC860 notation: CLK I LVTTL Address Bus: These leads are the address bus used by the host processor for accessing the PHAST-12N for a read or write cycle ...
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... LVTTL Local Address Bus: These leads are the address bus used by the host processor for accessing the PHAST-12N for a read or write cycle. MPA13 is the most significant bit in the location’s address. Motorola MPC8260 Notation: L_A[ ] PHAST-12N Device DATA SHEET TXC-06312B Name/Function Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... MPTS L3 I MPWR L2 I MPACK L1 O(T) LVCMOS MPINTR B3 O PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - Type LVTTL/ Local Data Bus: These leads are the bidirectional data bus LVCMOS used for transferring data between the PHAST-12N and the host 8mA processor. ...
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... This lead must be tied to VSS. I LVTTL Receive Line Bypass Sequence: For TranSwitch testing purposes. This lead must be tied to VSS. I LVTTL Receive Line Bypass Data: For TranSwitch testing purposes. These leads must be tied to VSS. PHAST-12N Device DATA SHEET TXC-06312B Name/Function Name/Function PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... AA4 BYPTXDATA00 AB2 TEST Symbol Lead No. DEVHIGHZ C4 TEST1 C3 PLLBYPASS A5 SCANEN D7 SCANMODE C6 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Lead Descriptions - - I/O/P Type I LVTTL Transmit Line Bypass Clock: For TranSwitch testing purposes. This lead must be tied to VSS. O LVCMOS Transmit Line Bypass C1 Indication: 8mA For TranSwitch testing purposes. ...
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... Pre-assembly storage in non-drypack conditions is not recommended. Please refer to the instructions on the “CAUTION” label on the drypack bag in which devices are supplied. 3. Test method for ESD per JEDEC JESD22-A114C.01. 4. Device core is 1.8V only. 5. All LVDS and LVPECL inputs, LINERXCAP and LINETXCAP are excluded. 7.2 THERMAL CHARACTERISTICS Parameter Thermal resistance - junction to ambient ...
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... Typical values are based on measurements made with nominal voltages Maximum values are based on measurements made at maximum voltages All four line interfaces are operational in STM-1/OC-3 mode, and the APS port is operational. 3. All measurements for the Parameter P PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Selected Parameter Values - ...
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... VSS required to provide a pull-up and a pull-down resistor at the LINETXDATAxP and LINETXDATAxN (x = 1...4) pins on the PHAST-12N: • pull-up value (towards +3.3V) = 130 • pull-down value (towards VSS Selected Parameter Values - PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Provide enough resistors in the schematic. Some of them may not be required, and can be treated as ‘do not install’. To achieve optimal jitter performance recommended to connect a differential oscillator to REFTXCLK2P/N (LVPECL), instead of a single-ended to REFTXCLK1 (LVTTL). LVPECL - PCB guidelines: The differential pairs (P and N) will be routed together, have a controlled impedance of 50 and be the same length ...
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... Unused LVDS inputs can be left floating (no resistors required). Unused LVDS outputs can be left floating (no resistors required Selected Parameter Values - cable careful implementation, cable length can PHAST-12N Device DATA SHEET TXC-06312B termination resistor between resistor on the board, between PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Rx input differential voltage input offset voltage iS Input/Output Parameters for LVDS Parameter Min 0.925 1.125 -. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 , O NPUT UTPUT AND Typ Max Unit 1.114 V 1.769 V 0.657 V 1.44 V TBD V 2.4 V Typ Max Unit 1.475 V V 0.4 V 1.275 V 140 Ohm 1.8 V ...
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... DD33 DD33 SS Test Conditions 3.14 < V < 3.46 DD33 3.14 < V < 3.46 DD33 DD33 Test Conditions 3.14 < V < 3.46 DD33 3.14 < V < 3.46 DD33 DD33 Test Conditions V = 3.15 -24 DD33 3.15 DD33 LOAD LOAD input . DD33 PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Output Parameters for LVCMOS 16mA Parameter Min Output capacitance 1.28 RISE t 1.04 FALL Leakage tristate Note: Open Drain requires use of a 4.7 k external pull-up resistor to V PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 - Typ Max Unit TBD 3.38 ns 3.22 ns ±15 A Typ Max Unit V ...
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... V < 3.45 DD33 3.15 < V < 3.45 DD33 0 to 3.3 V input V = 3.15 -16 DD33 3.15 DD33 LOAD LOAD Test Conditions 3.15 < V < 3.45 DD33 3.15 < V < 3.45 DD33 0 to 3.3 V input V = 3.15 DD33 3.15 DD33 LOAD LOAD PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... The waveforms shown correspond to the positive clock edge selection additional delay extra CBDPCLK clock cycles can be inserted between the Drop bus data/parity and the Drop bus timing signals, CBDPJ0J1 and CBDPSPE, see correspond to a delay of 0 clock cycles. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - 9 ...
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... Timing Characteristics - t PWH J1 pulse #1 J1 pulse # Symbol t CYC t PWH PHAST-12N Device DATA SHEET TXC-06312B J1 pulse #12 V1 pulse #1 V1 pulse #2 Min Typ Max Unit 12. CYC “Add Bus see “Add Bus Delay” on page 134. The PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... The waveforms shown correspond to the positive clock edge selection. An additional delay extra CBADCLK clock cycles can be inserted between the Add bus timing 4. signals, CBADJ0J1 and CBADSPE, and the Add bus data/parity, waveforms shown correspond to a delay of 1 clock cycle. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - ...
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... TOHRXALE/TOHRXADDR out valid delay from TOHRXCLK TOHRXDLE/TOHRXDATA out valid delay from TOHRXCLK Timing Characteristics - Figure 8. RX TOH Byte Interface t PWH A0 A8 Symbol t CYC t PWH t D(1) t D(2) PHAST-12N Device DATA SHEET TXC-06312B TOH DATA D(2) Min Typ Max Unit 12. CYC PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... TOHTXDATA (input Load Parameter TOHTXCLK clock period TOHTXCLK clock pulse width TOHTXALE/TOHTXADDR out valid delay from TOHTXCLK TOHTXDLE out valid delay from TOHTXCLK TOHTXDATA setup time before TOHTXCLK TOHTXDATA hold time after TOHTXCLK PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Figure 9 ...
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... POHRXCLK clock pulse width POHRXALE/POHRXADDR out valid delay from POHRXCLK POHRXDLE/POHRXDATA out valid delay from POHRXCLK Timing Characteristics - t PWH A6 A0 Symbol t CYC t PWH t D(1) t D(2) PHAST-12N Device DATA SHEET TXC-06312B POH DATA D(2) Min Typ Max Unit 12. CYC PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... POHTXDATA (Input Load Parameter POHTXCLK clock period POHTXCLK clock pulse width POHTXALE/POHTXADDR out valid delay from POHTXCLK POHTXDLE out valid delay from POHTXCLK POHTXDATA setup time before POHTXCLK POHTXDATA hold time after POHTXCLK PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - ...
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... LRPRXCLK clock period LRPRXCLK clock pulse width LRPRXFS/LRPRXDATA out valid delay from LRPRXCLK Timing Characteristics - t CYC t PWH last bit bit #1 bit # Symbol t CYC t PWH t D PHAST-12N Device DATA SHEET TXC-06312B bit #3 Min Typ Max Unit 51. CYC PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... LRPTXCLK (Input) LRPTXFS (Input) .... LRPTXDATA (Input Load Parameter LRPTXCLK clock period LRPTXCLK clock pulse width LRPTXFS/LRPTXDATA setup time before LRPTXCLK LRPTXFS/LRPTXDATA hold time after LRPTXCLK PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Figure 13. TX Line Ring Port Interface last bit bit #1 t ...
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... PRPRXCLK clock period PRPRXCLK clock pulse width PRPRXFS/PRPRXDATA out valid delay from PRPRXCLK Timing Characteristics - t CYC t PWH last bit bit #1 bit # Symbol t CYC t PWH t D PHAST-12N Device DATA SHEET TXC-06312B bit #3 Min Typ Max Unit 51. CYC PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Figure 15. TX Path Alarm Indication Port Interface PRPTXCLK (Input) PRPTXFS (Input) .... PRPTXDATA (Input Load Parameter PRPTXCLK clock period PRPTXCLK clock pulse width PRPTXFS/PRPTXDATA setup time before PRPTXCLK PRPTXFS/PRPTXDATA hold time after PRPTXCLK PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - last bit bit #1 bit # ...
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... Figure 16. Relationship Between the External Frame Reference Pulse (REFTXFS) and the Generated Internal Frame Reference Pulse (REFSYSFS) a. REFTXFS synchronous to rising edge of LINETXCLK (at 77.76 MHz) t (Output) CYC LINETXCLK (Output) REFTXFS (Input) REFSYSFS (Output) b. REFTXFS synchronous to falling edge of LINETXCLK (at 77.76 MHz) t CYC LINETXCLK ...
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... Notes: 1. The relationship between the External Frame Reference pulse input (REFTXFS lead) and System Frame Reference Pulse is only useful when LINETXCLK is configured to 77.76 MHz. Because of this the period of LINETXCLK used in the timing diagrams above is 12.86 ns additional offset 9719 clock cycles (77.76 MHz clock) can be inserted between REFTXFS and REFSYSFS by ...
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... D t PW_SYSFS Symbol t CYC t PWH t PW_SYSFS t OFFSET_ADD t OFFSET_DROP “Add Bus Delay” on page OFFSET_ADD PHAST-12N Device DATA SHEET TXC-06312B Min Typ Max Unit 12. CYC 12.86 12. CYC 26 t CYC Figure 7) can be inserted between the 134). When TimingDelay = 0, PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Figure 18. Microprocessor Interface: Generic Intel Mode Write Cycle t SU1 A t SU2 RD t SU3 CS t SU4 RDY CLK Note: MPACK (RDY) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Descriptions table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Generic Intel - Host Processor Interface ...
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... Delay from rising edge WR to inactive edge RDY Delay from RDY going inactive to RDY going in tristate Delay from rising edge WR to RDY going in tristate WR inactive pulse width Response latency CS inactive pulse width PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Figure 19. Microprocessor Interface: Generic Intel Mode Read Cycle t SU1 A t SU2 WR t SU3 RDY CLK Note: MPACK (RDY) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - SU4 Generic Intel - Host Processor Interface ...
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... Delay from RDY going inactive to RDY going in tristate Delay from rising edge RD to RDY going in tristate RD inactive pulse width Response latency Delay from falling edge driving Delay from rising edge going in tristate CS inactive pulse width PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Figure 20. Microprocessor Interface: Generic Motorola Mode Write Cycle t SU1 A t SU2 R/W t SU3 CS t SU4 DSACK CLK Note: MPACK (DSACK) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Generic Motorola - Host Processor Interface ...
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... Delay from rising edge DS to inactive edge DSACK Delay from DSACK going inactive to DSACK going in tristate Delay from rising edge DS to DSACK going in tristate DS inactive pulse width Response latency CS inactive pulse width PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
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... Figure 21. Microprocessor Interface: Generic Motorola Mode Read Cycle t SU1 A t SU2 R/W t SU3 DSACK CLK Note: MPACK (DSACK) is shown active low. This corresponds to MPACKLEVEL being tied low. 1. See the Lead Description table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - SU4 Generic Motorola - Host Processor Interface ...
Page 75
... Delay from DSACK going inactive to DSACK going in tristate Delay from rising edge DS to DSACK going in tristate DS inactive pulse width Response latency Delay from falling edge driving Delay from rising edge going in tristate CS inactive pulse width PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 76
... PHAST-12N Device DATA SHEET TXC-06312B Figure 22. Microprocessor Interface: Motorola MPC860 Mode Write Cycle CLK t SU1 A t SU2 RD/WR t SU3 SU4 See the Lead Description table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - t SU5 Motorola MPC860 - Host Processor Interface for the mapping to I/O leads. ...
Page 77
... Delay from rising edge CLK to active edge TA Delay from rising edge CLK to inactive edge TA Delay from TA going inactive to TA going in tristate Delay from rising edge CLK to TA going in tristate Maximum response latency PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 78
... PHAST-12N Device DATA SHEET TXC-06312B Figure 23. Microprocessor Interface: Motorola MPC860 Mode Read Cycle CLK t SU1 A t SU2 RD/WR t SU3 SU4 See the Lead Description table on PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - t SU6 Motorola MPC860 - Host Processor Interface for the mapping to I/O leads. ...
Page 79
... Delay from TA going inactive to TA going in tristate Delay from rising edge CLK to TA going in tristate Maximum response latency Setup time rising edge CLK Hold time of D going in tristate to rising edge CLK PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 80
... Figure 24. Microprocessor Interface: Motorola MPC8260 Local Bus Mode Write Cycle CLK t SU1 L_A t SU2 LWR t SU3 CS t SU5 LCL_D t D1 LGTA 1. See the Lead Description table on I/O leads. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Motorola MPC8260 Local Bus - Host Processor Interface ...
Page 81
... Delay from rising edge CLK to active edge LGTA Delay from rising edge CLK to inactive edge LGTA Delay from LGTA going inactive to LGTA going in tristate Delay from rising edge CLK to LGTA going in tristate Maximum response latency PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 82
... PHAST-12N Device DATA SHEET TXC-06312B Figure 25. Microprocessor Interface: Motorola MPC8260 Local Bus Mode Read Cycle CLK t SU1 L_A t SU2 LWR t SU3 CS LCL_D LGTA 1. See the Lead Description table on I/O leads. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - SU6 Motorola MPC8260 Local Bus - Host Processor Interface ...
Page 83
... Delay from LGTA going inactive to LGTA going in tristate Delay from rising edge CLK to LGTA going in tristate Maximum response latency Setup time D to rising edge CLK Hold time of D going in tristate to rising edge CLK PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 84
... TCK clock duty cycle t PWH/tCYC TMS setup time to TCK TMS hold time after TCK TDI setup time to TCK TDI hold time after TCK TDO delay from TCK TRS pulse width PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Timing Characteristics - - Figure 26. Boundary Scan Timing t H(1) ...
Page 85
... POH column VC-4-Xc resp. STS-Nc contiguous concatenated container. The AUG-1 time slot is a slave (i.e., it does not carry the POH column VC-4-Xc resp. STS-Nc contiguous concatenated container. PHAST-12N Device DATA SHEET TXC-06312B 10.0 O PERATION Figure 1. The mapping of PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 86
... Is_TUG_Structured 0 1 (Default) When TUG-3 is mapped in VC-4/AU-4 or VC-3 is mapped in AU-3 an extra register is provided to specify whether these containers contain TUG-2 or not. These configuration bits are don’t care for the VC-4’s containing C-4. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - AUG-1 AUG-1 ...
Page 87
... The Add Telecom Bus clock lead, CBADCLK input in slave timing mode. It gets retimed to the System Clock in the Retimer The System Clock is available on an output lead: LINETXCLK, optionally divided down to 19.44 MHz. The PHAST-12N’s internal Clock Recovery units, operating on the four SDH/SONET Receive Line interfaces and the Receive APS Port generate five recovered clocks: one for each channel ...
Page 88
... MHz • 622.08 MHz (bypass mode) The Rx timebase can be selected using control bits: • Either one of the two external Tx clock sources: REFTXCLK1 or REFTXCLK2P/N (External Timing) (control field TxRefSelect, see • The external Rx clock source: REFRXCLOCK (Line/Loop - Timing) (control field RxRef- ...
Page 89
... K1/K2 APS K1/K2 APS Pointer Tracking LINERXCLK1..4 Retimer High Order Path Cross Connect POH Monitor DROP Telecom Bus PHAST-12N Device DATA SHEET TXC-06312B APS Port @ 622.08 Mbit/s APS Port Receive K1/K2 APS Pointer Tracking APSRXCLK Retimer PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 90
... MPCLK System Clock (=LINETXCLK) LINERXCLK3 MPCLK System Clock (=LINETXCLK) LINERXCLK4 MPCLK System Clock (=LINETXCLK) APSRXCLK MPCLK System Clock (=LINETXCLK) CBADCLK PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - Memory Maps and Bit Descriptions). Blocks Global Control Reset Generator Interrupt Clock Recovery/Clock Synthesis/SerDes JTAG Master ...
Page 91
... AddCombus_Reset: Reset in the Add Combus clock domain • RxLine1_Reset ... RxLine4_Reset: Reset in the RxLine 1 ... 4 clock domain These software resets may only be asserted when RESETH is equal to 0x91. They may be deasserted at anytime Operation - PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B June 2005 ...
Page 92
... Set device in software reset: Write 0x91 to RESETH (Address 0x00A0). Other clock domains can also be set in reset now (See Memory Map). • Write 0x0000 to IndirectAccessMode (Address 0x3A26), followed by writing 0x0017 to IndiretAccessData (Address 0x3A5E) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - Memory Maps and Bit Descriptions CDR/CS) ...
Page 93
... RxPLL_PowerDown (Address 0x3A72) LineRate (Address 0x3A52) OC3NotOC12 STM-1/OC-3 Mode (Address 0x3A5A) 0x0F • Write 0x00 to TxRefClock2 PadPowerDown register (Address 0x3A34) if REFTXCLK2 is used as reference clock Operation - External Timing 0x0 N/A Select timing mode channel Select Rx Reference Clock Enable/Disable External Capacitor for ...
Page 94
... SerDes_LoadConfig will be reset automatically by the device after the transfer is completed (approx. 420 microprocessor clockcycles). Note however settings to other addresses than those before mentioned are still possible during this transfer. The configured registers will not be reset after transfer. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - ...
Page 95
... PRBS generator and analyzer before (re-)configuring them. Important Notes: 1. Although the PRBS bit error counter is mapped in the memory map of the CDR/CS block, the System clock (LINETXCLK) must be available when reading this counter may contain errors not recalculated on the PRBS data ...
Page 96
... A single 622.08 Mbit/s LVDS serial APS interface with differential input/output is provided. Clock recovery and synthesis are integrated. The device’s System Clock is the time base for the transmit APS interface output. The APS port interface can be powered down via a memory mapped register. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - ...
Page 97
... Loss of Lock (LOL) of the on-chip clock and data recovery will be reported • Frame alignment is recovered from the A1-A2 bytes of the received signals • Errors in the frame alignment signal will be detected and reported as OOF Operation - Status Req PHAST-12N Device DATA SHEET TXC-06312B 270 Payload PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 98
... B1 byte of the current frame before scrambling. The software con- figurable B1 byte has a special behavior, in that the filled in byte is used as an error-mask to corrupt the calculated B1 byte. • The D1-D3 bytes will optionally be inserted from PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - ...
Page 99
... The PHAST-12N RSOH Monitor will insert AIS per line interface towards the MSOH Monitor according to the following expression: aAIS = [line Operation - dTIM * not TIM_AIS_Insert_Disable [line] RSOH_AIS_Force [line] PHAST-12N Device DATA SHEET TXC-06312B [line] PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 100
... STM-n frame are detected by the BIP-nx24. Optionally bit errors will be counted • The error count per frame will be forwarded to the internal and external line ring ports as REI indication for the mate TOH generator PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - ...
Page 101
... EXC_AIS_Insert_Disable [line] dSSF * not SSF_AIS_Insert_Disable [line] MSOH_AIS_Force [line] dAIS * not AIS_RDI_Insert_Disable [line] dEXC * not EXC_RDI_Insert_Disable [line] dSSF * not SSF_RDI_Insert_Disable [line] MSOH_AIS_Force [line] PHAST-12N Device DATA SHEET TXC-06312B [line] [line] [line] [line] [line] [line] PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 102
... APS Port • POH Termination Each bus will transport synchronous payload containers equivalent to a STM-4/OC-12 rate, i.e AU-3/VC-3/STS-1’ four VC-4/STS-3c’s SPE two STS-6c’s, one STS-9c, one VC-4-4c/STS-12c, SPE or combinations thereof. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - Description ...
Page 103
... Status: the status of the received line, including the signal failure and signal degrade con- ditions Operation - Extra Traffic To/From POH Monitor/Generator PHAST-12N Device DATA SHEET TXC-06312B Cross Connect Switch y Bridge Squelch Extra Protected Traffic Traffic PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 104
... It will also monitor the in-band forwarded of RxAPS, TxAPS, Status and Request indications. The TxAPS will be forwarded to the TOH Generator. The latter will have an option to insert the transmitted K1/K2 APS autonomously from the TxAPS on the Rx APS Port or from software controlled registers. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - ...
Page 105
... Receive APS Port interface which transports the payload of the received Protection line. W TxApsPort y RxApsPort W Protected Traffic Operation - “APS Interface” on page P W TxApsPort y Switch RxApsPort W Protected Traffic Figure 30. STM-4/OC-12, 1+1 APS PHAST-12N Device DATA SHEET TXC-06312B 96, the presence P TxApsPort TxApsPort RxApsPort RxApsPort PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 106
... Protection line. The Worker PHAST-12N performs the protection switch. It connects the protected traffic to the Receive APS Port interface which transports the payload of the received Protection line. The unprotected extra traffic is no longer available and will be squelched. W TxApsPort y RxApsPort W Protected Traffic PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - TxApsPort Switch ...
Page 107
... Protection line available at the Receive APS Port interface Operation - W4 PHAST-12N #1 PHAST-12N #2 RxApsPort TxApsPort y RxApsPort TxApsPort W4 PHAST-12N Device DATA SHEET TXC-06312B Cross Connect device #2 Figure 33, the PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 108
... This allows unprotected extra traffic to be transported over a Protection line while there is no protection request active at that line Cross Connect device # Protected Traffic To/From POH Monitor/Generator Figure 34. STM-1/OC-3, 1:1 APS Idle State PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation - - W4 PHAST-12N #1 PHAST-12N #2 RxApsPort TxApsPort y RxApsPort TxApsPort W4 W4 PHAST-12N #1 PHAST-12N #2 ...
Page 109
... W2 W3 Protected Traffic To/From POH Monitor/Generator Figure 35. STM-1/OC-3, 1:1 APS Switch State Operation - W4 PHAST-12N #1 PHAST-12N #2 RxApsPort TxApsPort y TxApsPort RxApsPort W4 PHAST-12N Device DATA SHEET TXC-06312B Figure 35, the Bridge Cross Connect y device # Squelch Extra Traffic To/From POH Monitor/Generator PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 110
... It connects the protected traffic of the failed line to the payload of its associated received Protection line available at the Receive APS Port interface. The unprotected extra traffic of that Protection line is no longer available and will be squelched. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Operation ...
Page 111
... PHAST-12N #2 TxApsPort RxApsPort y y RxApsPort TxApsPort W4 PHAST-12N Device DATA SHEET TXC-06312B Bridge Cross Connect device #2 Squelch Extra Traffic Protected Traffic To/From POH Monitor/Generator Switch y Cross Bridge Connect device #2 Squelch Extra Traffic Protected Traffic To/From POH Monitor/Generator PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 112
... Important note: This concatenation detector only detects the concatenation indicators of the incoming pointer bytes. The detected configuration only serves as status, reported to software and is never used to configure the pointer tracking process. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 P T ...
Page 113
... The System Frame Reference Pulse will still be generated during LOF state, locked on previously accepted Frame Pulse Pointer Tracking Retimer High Order Path Cross Connect POH Retimer ADD Figure 17. PHAST-12N Device DATA SHEET TXC-06312B Pointer Tracking Retimer PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 114
... If the FIFO is almost empty or almost full, immediate action is required. These filling levels are called Immediate Leak Zone. This zone is 4 words wide at each end of the filling level. If the PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Figure 40. ...
Page 115
... The REI will be inserted into the G1 byte • Per high order path the RDI can be sourced from • The transmit POH RAM • The transmit POH byte interface • The internal or external ring port PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 116
... The F3 byte will be inserted from • The transmit POH RAM • The transmit POH byte interface • The K3 byte will be inserted from • The transmit POH RAM • The transmit POH byte interface PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 E-RDI indication b5 Server 1 ...
Page 117
... If one or more errors are indicated by the REI G1, the FarEndDefect_Counter will be updated. • Optionally bit errors will be counted “Trail Trace Identifier Process” on page 137 “BER Supervision for B2/B3” on page 134 “BER Supervision for B2/B3” on page 134 PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 118
... The dLOM defect will be detected in case a low order multiframe is expected • Received K3 is debounced frame basis • Accepted K3 is reported • Changes in accepted K3 are reported • AIS will be inserted per high order path according to the following expression: aTSF [path] aAIS [path] PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 119
... TIM_RDI_Insert_Disable [path] dPLM * not PLM_RDI_Insert_Disable [path] aE-RDI-S [path] aE-RDI-C [path] [path] * not AIS_SSF_Contribution_Disable [path] [path] [path] + SSF_UNEQ_Inhibit_Disable) [path] + TTIZERO_UNEQ_Contribution_Disable) [path] + TIM_UNEQ_Contribution_Disable) [path] [path] + SSF_TIM_Inhibit_Disable) [path] * not UNEQ_TIM_Inhibit_Disable [path] * not TTIZERO_TIM_Inhibit_Disable [path] PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 120
... Optionally bypass the POH monitor: the entire high order path is passed through without processing. Note: The High order POH Monitor should be bypassed for unused high-order paths. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 [path] + SSF_TTIZERO_Inhibit_Disable) [path] [path] + SSF_DEG_Inhibit_Disable) [path] + TIM_DEG_Inhibit_Disable) ...
Page 121
... Note the BIP bytes (B1, B2) have a special meaning, these can be used as an error mask on the calculated BIP. The Transmit TOH Port consists of following leads: • Output Transmit TOH Port Clock TOHTXCLK • Output Transmit TOH Port Address Latch Enable TOHTXALE • Output Transmit TOH Port Address TOHTXADDR • ...
Page 122
... MS DCC bytes mode: the Transmit DCC port will request the MS DCC bytes DCC bytes mode: the Transmit DCC port will request the RS DCC bytes. The Transmit DCC Port consists of following leads: PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Figure 8): Table 32). The Receive TOH Port interface has to be enabled by the ...
Page 123
... High Order Pointer Tracking, Retiming and Pointer Generation - • Inputs Transmit DCC Data DCCTXDATA1..4 • Outputs Transmit DCC Clock DCCTXCLK1..4 The index indicates the port, one per transmit line. The Transmit DCC Clocks DCCTXCLK1..4 have a constant frequency and depend on the configured mode, as indicated in following table: ...
Page 124
... The Transmit Line Alarm Indication (Ring) Port Interface leads must then be connected to VSS. Figure 41 shows the use of the internal Line Alarm Indication (Ring) Port Interface. Figure 41. Internal Line Alarm Indication (Ring) Port Interface PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Tx Line Interface Rx Line Interface TOH ...
Page 125
... Output Receive Line Alarm Indication (Ring) Port data LRPRXDATA The Transmit Line Alarm Indication (Ring) Port Interface consists of following leads: • Input Transmit Line Alarm Indication (Ring) Port clock LRPTXCLK • Input Transmit Line Alarm Indication (Ring) Port frame sync LRPTXFS • ...
Page 126
... A6 High Order path number The least significant nibble identifies the POH byte on the High Order POH Port Interface The most significant nibble identifies the High Order path number PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 POH byte identification A1 A0 POH Byte VC-3/STS-1 SPE #1 or VC-4/STS-3c SPE #1 ...
Page 127
... POH port interface, while the B3 BIP-8 can be used as error mask on the calculated BIP-8 for test purposes. The Transmit POH Port consists of following leads: • Output Transmit POH Port Clock POHTXCLK • Output Transmit POH Port Address Latch Enable POHTXALE • Output Transmit POH Port Address POHTXADDR • ...
Page 128
... When the Remote Information is taken from the Transmit High Order Alarm Indication (Ring) Port Interface possible to configure the High Order Alarm Indication (Ring) Port Interface to use the internally or externally available information. When the ExtendRDI option is asserted, the RDI insertion will be extended to minimum 20 frames. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 - Figure 10): ...
Page 129
... High Order Alarm Indication (Ring) Port Interface. Figure 43. Internal High Order Alarm Indication (Ring) Port Interface High Order Path POH Generator High Order Alarm Indication (Ring) Port PHAST-12N Device DATA SHEET TXC-06312B PHAST-12N Rx High Order path POH Monitor aRDI REI PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 130
... Output Receive High Order Alarm Indication (Ring) Port data PRPRXDATA The Transmit High Order Alarm Indication (Ring) Port Interface consists of following leads: • Input Transmit High Order Alarm Indication (Ring) Port clock PRPTXCLK • Input Transmit High Order Alarm Indication (Ring) Port frame sync PRPTXFS • ...
Page 131
... Drop Bus Parity Selection 80) Odd parity is calculated for the data output leads CBDPD(7-0). Odd parity is calculated for the data and timing output leads, CBDPD(7-0), CBDPJ0J1 and CBDPSPE. PHAST-12N Device DATA SHEET TXC-06312B B ELECOM US “SDH/SONET Mapping” PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 132
... Input data CBADD(7-0) • Input parity CBADPAR The timing information can be input or output: • Input/Output clock CBADCLK • Input/Output J0, J1, and optional V1 marker pulses CBADJ0J1 • Input/Output payload indication CBADSPE PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - Drop Bus Parity Selection 80) Even parity is calculated for the data output leads CBDPD(7-0) ...
Page 133
... Active CBADCLK clock edge Output signals are clocked out on positive CBADCLK clock edge. Output signals are clocked out on negative CBADCLK clock edge. Add Bus Timing Mode Table 68. Other than an alarm indication, no action is taken by the PHAST-12N Device DATA SHEET TXC-06312B 85). PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 134
... For B2 (MSOH) an interval is declared bad if the number of errored blocks in that interval is greater than or equal to DEG_DetectionErrorThreshold. For B3 (POH) an interval is declared bad if the number of errored blocks in that interval is greater than DEG_DetectionErrorThreshold. Remark the slight difference between the B2 (MSOH) and B3 (POH) detectors configuration! PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - ...
Page 135
... BIP error counter can occur. For B2 (TOH) the BIP error counters have a saturating behaviour and are thus not vulnerable to this Telecom Bus - parameters DEG_DetectionErrorThreshold PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B and s or 125 ...
Page 136
... POH counters per high order path: • B3 near-end errored BIP count • B3 near-end errored block count • G1 far-end error count, configurable to count either REI errors or errored blocks • Near-end defect second • Far-end defect second PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - PHAST-12N ...
Page 137
... The following TTI message types are supported Telecom Bus - Repeating non-specific byte J0 Repeating specific byte 16-byte trace message Repeating non-specific byte J1 16-byte trace message 64-byte trace message with TFAS 64-byte trace message with CR/LF PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 138
... Defects representing the current status of the device are correlated to fault causes (correlated defects). This inhibition process avoids the unnecessary generation of interrupts, when a defect that high hierarchy leads to the generation of multiple lower order defects. Unlatched defects are read-only multiframe frames, depending on the TTI format. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - 1 ...
Page 139
... Telecom Bus - Defect_Latch not Defect_Mask i AND ( Summary not Summary_Mask i AND not General_Mask i AND OR APS_Interrupt not APS_Mask k AND ( HINT HINTEN ). AND ’ number of logical expressions ( PHAST-12N Device DATA SHEET TXC-06312B ) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 140
... TXC-06312B + = OR & = AND ~ = NOT index ranges range #VCs range #lines) Higher Order Pointer Tracker/ Retimer Interrupt Figure 46. High Order Point Tracker Retimer Interrupt Tree PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - MicroProcessor Interrupt (HINT & HINTEN) xor ~MPINTLEVEL General Interrupt APS Interrupt Figure 45. HINT CorrDefects_Summary.DetectedConcat_Event & ...
Page 141
... VC_Status[ho].CorrDefects_LatchedForInt.RDI_C & ~VC_Config{ho}.CorrDefects_Mask.RDI_C VC_Status[ho].CorrDefects_LatchedForInt.RDI_P & ~VC_Config{ho}.CorrDefects_Mask.RDI_P VC_Status[ho].CorrDefects_LatchedForInt.PLM & ~VC_Config{ho}.CorrDefects_Mask.PLM VC_Status[ho].CorrDefects_LatchedForInt.LOM & ~VC_Config{ho}.CorrDefects_Mask.LOM VC_Status[ho].CorrDefects_LatchedForInt.K3_APS & ~VC_Config{ho}.CorrDefects_Mask.K3_APS VC_Status[ho].CorrDefects_LatchedForInt.C2_Changed & ~VC_Config{ho}.CorrDefects_Mask.C2_Changed PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B June 2005 ...
Page 142
... PHAST-12N Device DATA SHEET TXC-06312B TOH Monitor General Interrupt TOH Monitor APS Interrupt PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - CorrDefects_LatchForInt.SignalDetect & ~CorrDefects_Mask.SignalDetect CorrDefects_LatchForInt.OOF & ~CorrDefects_Mask.OOF CorrDefects_LatchForInt.LOF & ~CorrDefects_Mask.LOF CorrDefects_LatchForInt.LOS & ~CorrDefects_Mask.LOS CorrDefects_LatchForInt.RSOHM_CI_SSF & ~CorrDefects_Mask.RSOHM_CI_SSF CorrDefects_LatchForInt.B1_Error & ~CorrDefects_Mask.B1_Error CorrDefects_LatchForInt.TIM & ~CorrDefects_Mask.TIM CorrDefects_LatchForInt.MSOHM_CI_SSF & ...
Page 143
... APS_Info(0).APSEvents_LatchedForInt.Status_Request_Changed & ~ APS_Info(0).APSEvents_Mask.Status_Request_Changed APS_Interrupts(Receive APS Line 2) & ~ APS_Interrupts_Mask(Receive APS Line 2) APS_Info(1).APSEvents_LatchedForInt.RX_K1K2_Changed & ~ APS_Info(1).APSEvents_Mask.RX_K1K2_Changed APS_Info(1).APSEvents_LatchedForInt.TX_K1K2_Changed & ~ APS_Info(1).APSEvents_Mask.TX_K1K2_Changed APS_Info(1).APSEvents_LatchedForInt.Status_Request_Changed & ~ APS_Info(1).APSEvents_Mask.Status_Request_Changed Figure 49. APS Interrupt Tree (part 1) PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 144
... PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - APS_Interrupts(Receive APS Line 3) & ~ APS_Interrupts_Mask(Receive APS Line 3) APS_Info(2).APSEvents_LatchedForInt.RX_K1K2_Changed & ~ APS_Info(2).APSEvents_Mask.RX_K1K2_Changed APS_Info(2).APSEvents_LatchedForInt.TX_K1K2_Changed & ~ APS_Info(2).APSEvents_Mask.TX_K1K2_Changed APS_Info(2).APSEvents_LatchedForInt.Status_Request_Changed & ~ APS_Info(2).APSEvents_Mask.Status_Request_Changed APS_Interrupts(Receive APS Line 4) & ~ APS_Interrupts_Mask(Receive APS Line 4) APS_Info(3).APSEvents_LatchedForInt.RX_K1K2_Changed & ...
Page 145
... CorrDefects_LatchForInt.FifoErrors[ho] & ~ CorrDefects_Mask.FifoErrors[ho] CorrDefects_LatchForInt.LOF & ~ CorrDefects_Mask.LOF GeneralInterrupts(Add Telecom Bus) & ~ GeneralInterrupts_Mask(Add Telecom Bus) Global_CorrDefects_LatchForInt.C1_LOF & ~ Global_CorrDefects_Mask.C1_LOF Global_CorrDefects_LatchedForInt.ParityError & ~ Global_CorrDefects_Mask.ParityError VCx_CorrDefects_Summary[ho] & ~ VCx_CorrDefects_SummaryMask[ho] VCx_CorrDefects_LatchForInt[ho].J1_LOF & ~ VCx_CorrDefects_Mask[ho].J1_LOF VCx_CorrDefects_LatchForInt[ho].V1_LOF & ~ VCx_CorrDefects_Mask[ho].V1_LOF PRELIMINARY TXC-06312B-MB, Ed. 2 PHAST-12N Device DATA SHEET TXC-06312B June 2005 ...
Page 146
... PHAST-12N Device DATA SHEET TXC-06312B Figure 52. General Interrupt Tree (part 2) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - GeneralInterrupts(POH Ring Port) & ~ GeneralInterrupts_Mask(POH Ring Port) CorrDefects_LatchForInt.CRC_Error & ~ Defects_Mask.CRC_Error CorrDefects_LatchForInt.LOC & ~ Defects_Mask.LOC GeneralInterrupts(Terminal POH Monitor) & ~ GeneralInterrupts_Mask(Terminal POH Monitor) POH Monitor Interrupt (Terminal Side) GeneralInterrupts(Line Pointer Tracker/Retimer) & ...
Page 147
... CDR_CS_Status_Mask(SignalDetect Line 3) CDR_CS_Status_LatchedForInt(SignalDetect Line 4) & ~ CDR_CS_Status_Mask(SignalDetect Line 4) CDR_CS_Status_LatchedForInt(Lock Indication PRBS Analyzer) & ~ CDR_CS_Status_Mask(Lock Indication PRBS Analyzer) Figure 53. General Interrupt Tree (part 3) Figure 54, one cell of a boundary scan register is assigned to each input Figure 26. PHAST-12N Device DATA SHEET TXC-06312B PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 148
... V Output and Input/Output Parameters’ section of this Data Sheet for worst case leakage currents of all devices sharing this pull-down resistor. PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Telecom Bus - - requirements listed in the ‘ ...
Page 149
... Telecom Bus - Boundary Scan Register CORE LOGIC OF DEVICE Instruction Register Bypass Register TAP Controller 3 TDI TDO Controls IN OUT Boundary Scan Serial Test Data Figure 54. Boundary Scan Schematic PHAST-12N Device DATA SHEET TXC-06312B Signal input and output leads PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 150
... High Order Path Ring Port/Alarm Interface 0x3F00 JTAG Master 0x3F80 Drop Telecom Bus 0x4000 POH Monitor - Rx Line Interface 0x4800 POH Monitor - Rx APS Interface 0x5000 POH Monitor - Terminal Side PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - M APS AND ...
Page 151
... The software must set this value to 0x1 as soon as it has finished the configuration of the device. 0x0 ro General purpose input (GPIN4..GPIN1). 0x0 rw General purpose output (GPOUT4..GPOUT1). PHAST-12N Device DATA SHEET TXC-06312B Description (See page 152) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 152
... Version 0x0006 Growth_Mask MaskLevel GrowthField 0x0008 Reserved PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_GLOBAL_CONTROL) Init Access 0x0 ro For every bit in the list, 0x1 means the RAMs of the corresponding clock domain are initialized, 0x0 the RAMs are not initialized. • ...
Page 153
... Reset is active as long as this register contains the value 0x91. Note: Only assert reset when RESETH = 0x91. Can be deasserted at any time. 0x0 rw Reserved PHAST-12N Device DATA SHEET TXC-06312B Description (See page 153) (See page 153) (See page 153) Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 154
... Bits Name 0x0000 APS_Interrupts_Mask 0x0004 IntCtrl_Config 0x0006 0 HINT 0x0008 0 HINTEN PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 6: Reset Generator (T_RGEN) Init Access 0x0 rw Microprocessor Controller Reset for Rx Line 1. Writing the value 0x91 to this register generates a reset in the Receive Line 1 clock domain ...
Page 155
... Reset is active as long this register contains the value 0x91. 0x3 0x0 = INT_LEVEL 0x1 = INT_RISING_EDGE 0x2 = INT_FALLING_EDGE 0x3 = INT_BOTH_EDGES Field to control on which edges the unlatched defects are latched for interrupts. 0x0 Reserved. PHAST-12N Device DATA SHEET TXC-06312B Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 156
... Name 0x0000 Enable 0 K1K2_ForwardEnable 1 SignalFail_ForwardEnable 2 SignalDegrade_ForwardEnable 0x0002 RX_K1K2_Data 0x0004 TX_K1K2_Data 0x0006 StatusRequest PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 9: Transmit APS Port (T_TX_APS) Init Access rw T_TX_APS_Common_Config General configuration. rw Array (4) of T_TX_APS_Config Offset between two elements = 0x8. Array index indicates the line (= line number - 1). ...
Page 157
... The corresponding VC-4 contains C-4 when ‘0’, the corresponding VC-4 contains three TUG-3’s when ‘1’. PHAST-12N Device DATA SHEET TXC-06312B Description (See page 157) (See page 158) (T_VCXPG_Common_Config) Description (See page 157) Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 158
... Name 0x0000 0 Force_AIS 1 Force_Uneq 2 Force_SupUneq 3 UniDirectional 4 OneBitRDI 5 Bypass PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init T_VCXPG_RAMBytes Configuration of the POH RAM bytes. T_VCXPG_Mode_record Mode Configuration. T_VCXPG_Control_record Source selection for the POH bytes. (T_VCXPG_RAMBytes) Init All 0x0 Array (64) of byte Offset between two elements = 0x2 ...
Page 159
... VCXPG_RAM = Use RAM as source • VCXPG_POH_INTF = Use POH Port Interface as source 0x0 0x0 = VCXPG_RAM 0x1 = VCXPG_POH_INTF Selects the source of the N1 Byte. • VCXPG_RAM = Use RAM as source • VCXPG_POH_INTF = Use POH Port Interface as source PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 160
... B2_BIP_BitErrors_MSB 0x0006 B2_BIP_BlockErrors 0x0008 REI_BIP_Errors 0x000A DefectSeconds 0 NearEndDefectSec 1 FarEndDefectSec PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 19: TOH Monitor (T_TOH_MONITOR) Init Access All 0x0 rw Array (16) of byte Offset between two elements = 0x2. Array index indicates the TTI byte number. ...
Page 161
... Degraded signal. 0x1 Excessive error. 0x1 Remote Defect Indication. 0x1 Line AIS detected on K2. 0x1 Signal Fail. 0x1 New (debounced) K1K2 value accepted. 0x1 New (debounced) S1 value accepted. PHAST-12N Device DATA SHEET TXC-06312B Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 162
... Debounce_K2_LSB_Separately 6 SignalDetect_LOF_Inhibit_Disable 7 LOS_LOF_Inhibit_Disable 8 SSF_AIS_Inhibit_Disable 0x0002 TTI_Config 0x0006 B2_Config PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOH_MONITOR_APS_Defects) Init 0x1 Signal Degrade. 0x1 Signal Fail. 0x1 New K1K2 value accepted. (T_TOH_MONITOR_Common_Config) Init 0x0 B1 BER performance counter reports bit errors when 0x1, block errors when 0x0 ...
Page 163
... When 0x0 the TTI message has to match the specified expected message (16 byte TTI message or repeating specific byte message). 0x5 Range Number of multiframes to set TIM alarm. 0x3 Range Number of multiframes to reset TIM alarm. PHAST-12N Device DATA SHEET TXC-06312B Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 164
... DEG_RecoveryWindowSize 0x000A EXC_DetectionErrorThreshold 0x000C EXC_DetectionWindowSize 0x000E EXC_RecoveryErrorThreshold 0x0010 EXC_RecoveryWindowSize PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOH_MONITOR_BIP_Detector_Config) Init 0x0 Assume Poisson error distribution when 0x1, bursty distribution when 0x0. T_BIP_PoissonDetector_Config Configuration for DEG/EXC detection, assuming Poisson distribu- tion of errors ...
Page 165
... TTI message for line 2 • bytes 32-47: TTI message for line 3 • bytes 48-63: TTI message for line 4 Note: Bytes are not used in STM-4 mode. PHAST-12N Device DATA SHEET TXC-06312B (T_Line_BIP_BurstyDetector_Config) Description Description (See page 166) (See page 167) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 166
... Offset Bits Name 0x0400 TOH_Contents Table 30: Transmit TOH Port Configuration Offset Bits Name 0x0000 0 TOH_Port_Enable PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_TOH_GENERATOR) Init Access See desc. rw Array (324) of nine_bits Offset between two elements = 0x2. Array index indicates the TOH byte number. ...
Page 167
... TOH_Events_LatchForInt descriptions for the layout of the bits. rw T_RXTDP_Common_Config General configuration. rw Array (4) of T_RXTDP_Line_Config Offset between two elements = 0x2. Array index indicates the line (= line number - 1). DCC port configuration. PHAST-12N Device DATA SHEET TXC-06312B Description Description (See page 169) (See page 169) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 168
... Bits Name 0x0280 TOH_Events_Summ ary 0x02C0 TOH_Events_Summ ary_Mask 0x0300 TOH_Events_LatchF orInt PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_RX_TOH_DCC_PORT) Init Access All 0x0 ro Array (4) of nine_bits Offset between two elements = 0x2. Array index indicates the summary of nine TOH_Events_LatchedForInt bits. ...
Page 169
... DCC port is enabled. 0x0 The DCC port is enabled when 0x1 and the RSOH_DCC_Port_Select setting determines which set of DCC bytes will be sent out on the DCC port (RS DCC or MS DCC). PHAST-12N Device DATA SHEET TXC-06312B Description Description (T_RXTDP_Line_Config) Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 170
... VCx Table 36: Pointer Tracker and Retimer Defect/Event Summary Offset Bits Name 0x0000 Summary 12 DetectedConcat_Event PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_HO_PTR_RETIMER) Init Access 0x1 rw Detected Concatenation event mask. 0x0 cow_1 Detected Concatenation event latched for interrupt. ...
Page 171
... SS bits to be used in the Pointer Generator. PHAST-12N Device DATA SHEET TXC-06312B (T_HOPTRRT_Common_Config) Description (T_HOPTRRT_VCx) Description (See page 171) (See page 172) (See page 172) (See page 172) (See page 172) (See page 172) (T_HOPTRRT_VC3_TUG3_Config) Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 172
... Table 42: Pointer Tracker and Retimer Defects Offset Bits Name 0x0000 0 AIS 1 LOP 2 Fifo_Error PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x10 Slow Leak Register (consult documentation). 0x10 Fast Leak Register (consult documentation). (T_HOPTR_VCx_Status) Init 0x0 Received SS bits reported by the Pointer Tracker. ...
Page 173
... Offset between external reference frame sync (REFTXFS) and system reference frame sync. 0x25E4 Reserved. 0x25E1 Reserved. PHAST-12N Device DATA SHEET TXC-06312B Description (See page 157) (See page 173) (See page 173) (See page 173) (See page 173) (See page 174) Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 174
... SS_bits 0x0002 SlowLeakRegister 0x0004 FastLeakRegister Table 48: Retimer Performance Counters Offset Bits Name 0x0000 OutgoingJustifications Outgoing_PJ Outgoing_NJ PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 46: Retimer Per Path (T_RT_VCx) Init Access rw T_RT_VC3_TUG3_Config High order path configuration. ro T_RT_PerfCounters Performance Counters. ...
Page 175
... Deserializer (CDR/CS). rw T_PLL_Control Control of the PLL’s in Clock Recovery, Serializer and Deserializer (CDR/CS). PHAST-12N Device DATA SHEET TXC-06312B (T_ANALOG) Description (See page 176) (See page 177) (See page 178) (See page 178) (See page 179) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 176
... Bits Name 0x0000 0 EnablePRBSGenerator PRBSGeneratorChannel 5 InvertPRBSGeneratorOutput 6 EnablePRBSAnalyzer PRBSAnalyzerChannel 11 InvertPRBSAnalyzerOutput PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Table 50: Test Configuration (T_TestControl) Init 0x0 Reserved. 0x0 Reserved. 0x0 Reserved. 0x0 Reserved. 0x0 Reserved. 0x0 Reserved. T_AUG1_Mode_Config AUG-1 mode configuration for the PRBS generator/analyzer at the cross connect ...
Page 177
... Line 2 • bit 2: Line 3 • bit 3: Line 4 • bit 4: APS 0x0 Selects the mode for the IndirectAccessData register. • 0x0: Mode0 • 0x8: Mode1 • All others: Reserved PHAST-12N Device DATA SHEET TXC-06312B Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 178
... Line 3 • bit 3: Line 4 • bit 4: APS 0x1 Power Down for the Transmit Reference Clock Pad, REFTXCLK2. The pad is powered down when 0x1. Init 0x3FF Power down for the SerDes transmit section. Must be set to 0x0 at power-up. 0x0 Indicates the line rate for the selected line when line timing is used. ...
Page 179
... MHz, REFTXCLK1 or REFTXCLK2 • 0x2: 155.52 MHz, REFTXCLK2 • 0x3: 622.04 MHz, REFTXCLK2. In this mode the Transmit PLL must be bypassed. Mind the Transmit PLL is actually still working then, although it’ s out- put is never used. 0x0 Receive PLL reference clock frequency. ...
Page 180
... CorrDefects_Unlatched 0x0028 CorrDefects_LatchForInt 0x0030 CorrDefects_Mask 0x0038 B1_PM_Counter 0x0040 APS_Info PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x4 Reserved. Set to 0x4 for STM-4/OC-12 application Set to 0x1 for STM-1/OC-3 application 0x4A Reserved. Set to 0x4a for STM-4/OC-12 application Set to 0x5c for STM-1/OC-3 application Init 0x4 Reserved ...
Page 181
... SF and bit 1 is SD), least significant byte is switch/bridge request). PHAST-12N Device DATA SHEET TXC-06312B (T_RX_APS_Common_Config) Description Description Description (See page 181) (See page 182) (See page 182) (See page 182) Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 182
... APS_Config Table 65: Cross Connect Bus Configuration Offset Bits Name 0x0000 AUG1 0x0002 Timeslot PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_RX_APS_APSBytes_Event) Init 0x1 Receive K1/K2 changed. 0x1 Transmit K1/K2 changed. 0x1 Status/Request information changed. Table 64: Cross Connect ...
Page 183
... Correlated defects mask. PHAST-12N Device DATA SHEET TXC-06312B (T_XConnect_Config) Description Description (See page 184) (See page 184) (See page 184) (See page 184) (See page 184) (See page 184) (See page 185) (See page 185) (See page 185) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 184
... VC3_TUG3_Mode_Config Table 71: Telecom Bus Path Configuration Offset Bits Name 0x0000 Is_TUG_Structured 0x0002 Reserved PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_DICB_Global_CorrDefects) Init 0x1 C1 Loss Of Frame. 0x1 Parity Error on the Telecom Bus. (t_dicb_VCx_CorrDefects_Summary) Init 0xFFF Defect Summary, one bit per high order path. Least significant bit corresponds to the first high order path ...
Page 185
... CRC error on external Ring Port interface. 0x1 Loss of clock on external Ring Port interface. PHAST-12N Device DATA SHEET TXC-06312B Description Description (See page 185) (See page 185) (See page 185) (See page 185) (See page 186) (T_HOPR_Common_Config) Description (T_HOPR_Defects) Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 186
... TDO_Fifo_B3 0x0030 TDO_Fifo_B4 0x0032 0 Start 0x0034 Done PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x0 Select external ring port when 0x1. Internal ring port is used when 0x0. 0x0 Resets an entire VC information when 0x1. 0x0 Extends RDI for 20 frames when 0x1. ...
Page 187
... Negative clock edge when 0x1, positive clock edge when 0x0. 0x0 Configure the delay between data and timing on the Add Combus. 0x1 Reserved. 0x0 Reserved. PHAST-12N Device DATA SHEET TXC-06312B Description Description (See page 187) (See page 187) Description Description PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 188
... VC_Config 0x0200 Common_Config 0x0300 Common_Status 0x0400 VC_Status PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x0 Calculate parity over data only, or over Data and Timing. Timing is included when 0x1. 0x0 Even parity when 0x1, odd parity when 0x0. ...
Page 189
... H4_MF_LO = Low Order Multiframe tracking 0x5 Number of ms that the OOM state must persist to declare the LOM defect. T_VCXPM_Defects Correlated defects mask. PHAST-12N Device DATA SHEET TXC-06312B (T_VCXPM_Config) Description (See page 190) (See page 190) (See page 191) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 190
... Name 0x0000 DEG_DetectionErrorThreshold 0x0002 DEG_DetectionWindowSize 0x0004 DEG_RecoveryErrorThreshold 0x0006 DEG_RecoveryWindowSize PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_VCXPM_ExpectedBytes) Init All 0x0 Array (64) of byte Offset between two elements = 0x2. Array index indicates the TTI byte number. Expected TTI message. ...
Page 191
... Inhibition of TIM defect by UNEQ defect is disabled when 0x1. 0x0 Inhibition of TIM defect by TTIZERO defect is disabled when 0x1. 0x0 Inhibition of TTIZERO defect by SSF defect is disabled when 0x1. PHAST-12N Device DATA SHEET TXC-06312B Description (T_VCXPM_Common_Config) Description (See page 157) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 192
... AIS_SSF_Contribution_Disable 12 TSF_PLM_Inhibit_Disable 13 TSF_LOM_Inhibit_Disable 14 PLM_LOM_Inhibit_Disable 0x000C Summary_Mask PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - Init 0x5 Range Number of consecutive mismatched multiframes to set TIM. 0x3 Range Number of consecutive match multiframes to clear TIM. 0x0 Insertion of AIS on incoming Server Signal Fail is disabled when 0x1. ...
Page 193
... T_VCXPM_Defects Correlated defects. T_VCXPM_Defects Correlated defects latched for interrupt. 0x0 Reserved. 0x0 Reserved. 0x0 Reserved. PHAST-12N Device DATA SHEET TXC-06312B Description (See page 193) Description Description (See page 194) 194) (See page 191) (See page 191) PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 194
... NearEndDefect_BitCounter 0x0004 FarEndDefect_Counter 0x0006 DefectSec 0 NearEndDefectSec 1 FarEndDefectSec PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Memory Maps and Bit Descriptions - (T_VCXPM_POH_Status) Init 0x0 J1 byte of the previously received frame. 0x0 Errored bit positions in B3 byte of the previously received frame. 0x0 C2 byte of the previously received frame. ...
Page 195
... The PHAST-12N device is packaged in a 376-lead mm, plastic ball grid array package suitable for surface mounting, as illustrated in E2 TRANSWITCH TXC-06312BIOG D D2 E1/4 D1/4 A2 (A3) Notes: 1. All dimensions are in millimeters. Values shown are for reference only. 2. Identification of the solder ball A1 corner is contained within this shaded zone. Package corner may not angle ...
Page 196
... Figure 56. STM-4/OC- STM-1/OC-3 Terminal Mux SDH/SONET STM-4/OC- STM-1/OC-3 SDH/SONET STM-4/OC- STM-1/OC-3 Figure 57. STM-4/OC- STM-1/OC-3 1+1, 1:1 APS Terminal Mux PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 A PPLICATION PHAST-12N 77.76 MHz EtherMap Telecom Bus TXC-06312B PHAST-12N 77.76 MHz Telecom Bus TXC-06312B Working Protected Traffic ...
Page 197
... VTXP -12 TEMx28 x-connect Telecom Telecom Bus Bus 77.76 77.76 MHz MHz VTXP-12 EtherMap x-connect Telecom Telecom Bus Bus SDRAM SDRAM PHAST-12N Device DATA SHEET TXC-06312B E1/T1 LIU ® 10/100 or Multi- ® - GMII PHY Control Processor PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 198
... PHAST-12N Device DATA SHEET TXC-06312B Part Number: TXC-06312BIOG376-Lead Plastic Ball Grid Array Package TL3M Device (Triple Level 3 Mapper). Maps three 44.736 Mbit/s DS3 to an STM-1, TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. A 34.368 Mbit/s E3 signal is mapped STM-1 TUG-3. The TL3M’s SDH/SONET interface format is 19.44 MHz Telecom Bus, a byte wide parallel ...
Page 199
... Fax: 3 3438 3698 Tel: Tel: Fax: (303) 397-2740 Web: Tel: Fax Web: PHAST-12N Device DATA SHEET TXC-06312B S OURCES (212) 642-4900 www.ansi.org (415) 561-6275 www.atmforum.com 20 7837 7882 3 3438 3694 (800) 854-7179 (within U.S.A.) (303) 397-7956 (outside U.S.A.) www.global.ihs.com www.etsi.org PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 ...
Page 200
... Corporate Place Rm 3A184 Piscataway, NJ 08854-4157 TTC (Japan): TTC Standard Publishing Group of the Telecommunication Technology Committee Hamamatsu-cho Suzuki Building 1-2-11, Hamamatsu-cho, Minato-ku Tokyo 105-0013, Japan PRELIMINARY TXC-06312B-MB, Ed. 2 June 2005 Tel: (800) 669-6857 (within U.S.A.) Tel: (903) 769-3717 (outside U.S.A.) Fax: (903) 769-3818 Web: www ...