SSTVF16857YG-T

Manufacturer Part NumberSSTVF16857YG-T
ManufacturerIDT, Integrated Device Technology Inc
SSTVF16857YG-T datasheets

Availability: By request

International delivery:

Warranty: 60 days

Shipping & payment terms

Added to cart

 

Specifications of SSTVF16857YG-T

Lead Free Status / Rohs StatusCompliant  
1
Page 1
2
Page 2
3
Page 3
4
Page 4
5
Page 5
6
Page 6
7
Page 7
8
Page 8
Page 1/8

Download datasheet (125Kb)Embed
Next
Integrated
Circuit
Systems, Inc.
DDR 14-Bit Registered Buffer
Recommended Applications:
DDR Memory Modules
Provides complete DDR DIMM logic solution with
ICS93V857 or ICS95V857
SSTL_2 compatible data registers
Product Features:
Differential clock signal
Meets SSTL_2 signal data
Supports SSTL_2 class I & II specifications
Low-voltage operation
- V
= 2.3V to 2.7V
DD
48 pin TSSOP and TVSOP package
1
Truth Table
n I
p
u
s t
R
E
S
E
T
#
C
L
K
C
L
K
#
X
r o
X
r o
L
F
o l
t a
n i
g
F
o l
t a
n i
g
H
H
H
L
r o
H
L
r o
H
Notes:
1.
H = High Signal Level
L = Low Signal Level
= Transition LOW-to-HIGH
= Transition HIGH -to LOW
X = Irrelevant
2.
Output level before the indicated
steady state input conditions were
established.
0746—10/28/02
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals.
ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.
Q
O
u
p t
u
s t
D
Q
X
r o
L
F
o l
t a
n i
g
H
H
4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)
L
L
) 2 (
X
Q
0
Block Diagram
38
CLK
39
CLK#
RESET#
48
D1
35
VREF
ICSSSTVF16857
Advance Information
Pin Configuration
1
48
Q1
2
47
Q2
3
46
GND
4
45
VDDQ
5
44
Q3
6
43
Q4
7
42
Q5
8
41
GND
9
40
VDDQ
10
39
Q6
11
38
Q7
12
37
VDDQ
13
36
GND
14
35
Q8
15
34
Q9
16
33
VDDQ
17
32
GND
18
31
Q10
19
30
Q11
20
29
Q12
21
28
VDDQ
22
27
GND
23
26
Q13
24
25
Q14
48-Pin TSSOP & TVSOP
6.10 mm. Body, 0.50 mm. pitch = TSSOP
34
R
CLK
D1
To 13 Other Channels
D1
D2
GND
VDD
D3
D4
D5
D6
D7
CLK#
CLK
VDD
GND
VREF
RESET#
D8
D9
D10
D11
D12
VDD
GND
D13
D14
1
Q1

SSTVF16857YG-T Summary of contents

  • Page 1

    Integrated Circuit Systems, Inc. DDR 14-Bit Registered Buffer Recommended Applications: • DDR Memory Modules • Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 • SSTL_2 compatible data registers Product Features: • Differential clock signal • Meets SSTL_2 signal ...

  • Page 2

    ICSSSTVF16857 Advance Information General Description The 14-bit ICSSSTVF16857 is a universal bus driver designed for 2.3V to 2.7V V except for the LVCMOS RESET# input. Data flow from controlled by the differential clock (CLK/CLK#) and a ...

  • Page 3

    Absolute Maximum Ratings Storage Temperature . . . . . . . . . . . . . . . . . . . . –65°C to +150°C Supply Voltage . . . . . . . . . . ...

  • Page 4

    ICSSSTVF16857 Advance Information Electrical Characteristics - 70º 2.5 +/-0.2V SYMBOL PARAMETERS All Inputs V I Standby (Static) ...

  • Page 5

    Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) SYMBOL PARAMETERS f Clock frequency clock t Clock to output time PD t Reset to output time RST t Output slew rate SL Setup time, fast slew rate ...

  • Page 6

    ICSSSTVF16857 Advance Information LVCMOS RESET DDQ Input t inact I DD (see note 2) 10% Voltage and Current Waveforms Inputs Active and Inactive Times t w Input V REF Voltage Waveforms - Pulse Duration Timing Input t S ...

  • Page 7

    ... INDEX INDEX AREA AREA aaa 6.10 mm. Body, 0.50 mm. pitch TSSOP (0.020 mil) (240 mil) Ordering Information ICSSSTVF16857yG-T Example: ICS XXXX PPP - T 0746—10/28/02 c SYMBOL aaa VARIATIONS - SEATING SEATING 48 PLANE PLANE Ref erence Do c.: JEDEC Pub licat O-153 Designation for tape and reel packaging ...

  • Page 8

    ICSSSTVF16857 Advance Information INDEX INDEX AREA AREA 4.40 mm. Body, 0.40 mm. pitch TSSOP (16 mil) (173 mil) Ordering Information ICSSSTVF16857yL-T Example: ICS XXXX ...