LU82551ITQ810 Intel, LU82551ITQ810 Datasheet

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... In addition, this device has been tested and conforms to the same parametric specifications as previous versions of the device. For more information regarding lead-free products from Intel Corporation, contact your Intel Field Sales representative. Datasheet — Full pin compatibility with the 82559 and 82559ER controllers — ...

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... Information in this document is provided in connection with Intel products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Intel's Terms and Conditions of Sale for such products, Intel assumes no liability whatsoever, and Intel disclaims any express or implied warranty, relating to sale and/or use of Intel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right ...

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Contents 1.0 Introduction......................................................................................................................... 1 1.1 Overview ............................................................................................................... 1 1.2 Byte Ordering ........................................................................................................ 1 1.3 References ............................................................................................................ 1 1.4 Product Ordering Codes........................................................................................ 2 2.0 Architectural Overview ....................................................................................................... 3 2.1 Parallel Subsystem Overview................................................................................ 3 2.2 FIFO Subsystem Overview ................................................................................... 3 2.3 10/100 ...

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Networking Silicon 5.7 Media Independent Interface (MII) Management Interface ................................. 34 6.0 Physical Layer Functional Description ............................................................................. 35 6.1 100BASE-TX PHY Unit ....................................................................................... 35 6.1.1 100BASE-TX Transmit Clock Generation .............................................. 35 6.1.2 100BASE-TX Transmit Blocks ............................................................... 35 6.1.3 ...

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Receive Direct Memory Access Byte Count........................................... 56 8.1.9 Flow Control Register............................................................................. 56 8.2 Statistical Counters ............................................................................................. 57 9.0 PHY Unit Registers ..........................................................................................................61 9.1 MDI Registers ............................................................................................. 61 9.1.1 Register 0: Control Register .................................................................. 61 9.1.2 Register ...

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Networking Silicon 12.0 Package and Pinout Information ...................................................................................... 89 12.1 Package Information ........................................................................................... 89 12.2 Pinout Information ............................................................................................... 91 12.2.1 Pin Assignments ................................................................................... 91 12.2.2 Ball Grid Array Diagram ......................................................................... 93 13.0 Reference Schematics ..................................................................................................... 94 vi Datasheet ...

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... Fast Ethernet Controller family. 1.1 Overview The 82551IT is an evolutionary addition to Intel’s family of 8255x controllers. It provides excellent performance by offloading TCP, UDP and IP checksums and supports TCP segmentation off-load for operations such as Large Send. The 82551IT provides an extended operating temperature in addition to all of the same capabilities and features as the 82551ER to address applications requiring a wider operating temperature range ...

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Networking Silicon 1.4 Product Ordering Codes Product ordering codes for the 82551IT Fast Ethernet PCI controller: • GD82551IT (Leaded) • LU82551IT (Lead Free) Device Stepping LU82551IT LU82551IT GD82551IT GD82551IT Figure 1. 82551IT Component Markings Legend: GRP1LINE1 - 82551IT ...

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... Architectural Overview ® The Intel 82551IT is divided into four main subsystems: a parallel subsystem, a FIFO subsystem, a 10/100 Mbps Carrier Sense Multiple Access with Collision Detect (CSMA/CD) unit, and a 10/ 100 Mbps physical layer (PHY) unit. 2.1 Parallel Subsystem Overview The parallel subsystem is comprised of several functional blocks: a PCI bus master interface, a micromachine processing unit and its corresponding microcode ROM, and a PCI Target Control/ Flash/EEPROM interface ...

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Networking Silicon • Tunable transmit FIFO threshold allows elimination of underruns while concurrent transmits are being performed. • Extended PCI zero wait state burst accesses to and from the 82551IT for both transmit and receive FIFOs • Efficient ...

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... Performance Enhancements All of Intel’s Fast Ethernet controllers have the ability to support full wire speeds. The 82551IT has been designed to provide improved networking throughput. Performance is limited to the system’s ability to feed data to the network controller. As networks grow, the task of servicing the network becomes a large burden on the platform. ...

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Networking Silicon 3.3 Hardware Integrity Support Cabling problems are a common cause for network downtime situations. Hardware Integrity (HWI) can help reduce this by locating cabling problems. It uses transmission line theory to measure the arrival time and ...

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Signal Descriptions 4.1 Signal Type Definitions Table 2. Signal Type Descriptions Type Name IN Input OUT Output TS Tri-State STS Sustained Tri-State OD Open Drain AI Analog Input AO Analog Output B Bias Digital Power DPS Supply Analog Power ...

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Networking Silicon 4.2 PCI Bus Interface Signals 4.2.1 Address and Data Signals Table 3. Address and Data Signals Symbol Type AD[31:0] TS C/BE#[3:0] TS PAR TS 4.2.2 Interface Control Signals Table 4. Interface Control Signals Symbol Type FRAME# ...

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Table 4. Interface Control Signals Symbol Type IDSEL IN DEVSEL# STS REQ# TS GNT# IN INTA# OD SERR# OD PERR# STS 4.2.3 System and Power Management Signals Table 5. System and Power Management Signals Symbol Type CLK IN IN/OUT CLK_RUN# ...

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Networking Silicon Table 5. System and Power Management Signals Symbol Type ISOLATE# IN ALTRST VIO IN 4.3 Local Memory Interface Signals Note: All unused Flash Address and Data pins MUST be left floating. Some of these ...

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Table 6. Local Memory Interface Signals Symbol Type FLA6:2 OUT FLA1/ TS AUXPWR FLA0/ TS PCIMODE# EECS OUT FLCS# OUT FLOE# OUT FLWE# OUT 4.4 Test Port Signals Table 7. Test Port Signals Symbol Type TEST IN TCK IN TI ...

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Networking Silicon 4.5 PHY Signals Table 8. PHY Signals Symbol Type TDP AO TDN RDP AI RDN ACTLED# OUT LILED# OUT SPDLED# OUT RBIAS100 B RBIAS10 B VREF B a. Based on some board ...

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Power and Ground Signals Table 9. Power and Ground Signals Symbol Type VCC DPS VCCR APS VSSPL, VSSPP, DPS VSSPT, VSS NC DPS Datasheet Name and Function Digital 3.3 V Power. The VCC pins should be connected to the ...

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Networking Silicon Note: This page is intentionally left blank. 14 Datasheet ...

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Media Access Control Functional Description 5.1 Device Initialization The 82551IT has six sources for initialization. They are listed according to their precedence: 1. Internal Power-on Reset (POR) 2. ALTRST# pin 3. RST# pin 4. ISOLATE# pin 5. Software Reset ...

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Networking Silicon Table 10. Initialization Effects Internal POR Power management event reset Statistic counters reset Sampling of configuration input pins 5.2 PCI Interface 5.2.1 Bus Operations After configuration, the 82551IT is ready for its normal operation ...

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Control/Status Register (CSR) Accesses The 82551IT supports zero wait state single cycle memory or I/O mapped accesses to its CSR space. Separate BARs request memory space and 64 bytes of I/O space to accomplish these accesses. ...

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Networking Silicon Figure 3. CSR I/O Write Cycle CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# STOP# Write Accesses: The CPU, as the initiator, drives the address lines AD[31:0], the command and byte enable lines C/BE#[3:0] and the control ...

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Flash Buffer Accesses The CPU accesses to the Flash buffer are very slow and the 82551IT issues a target-disconnect at the first data access. The 82551IT asserts the STOP# signal to indicate a target-disconnect. The figures below illustrate memory ...

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Networking Silicon Figure 5. Flash Buffer Write Cycle CLK FRAME# AD C/BE# IRDY# TRDY# DEVSEL# STOP# Write Accesses: The CPU, as the initiator, drives the address lines byte enable lines C/BE#[3:0] and with valid data immediately after asserting ...

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Retry Premature Accesses The 82551IT responds with a Retry to any configuration cycle accessing the 82551IT before the completion of the automatic read of the EEPROM. The 82551IT may continue to Retry any configuration accesses until the EEPROM read ...

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Networking Silicon Note: The 82551IT detects a system error for any parity error during an address phase, whether or not it is involved in the current transaction. 5.2.1.2 Bus Master Operation As a PCI Bus Master, the 82551IT ...

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For all write accesses to the control structure, the 82551IT uses the Memory Write (MW) command. For write accesses to data structure, the 82551IT may use either the Memory Write or Memory Write ...

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Networking Silicon 6. The MWI Enable bit in the 82551IT Configure command must be set to 1b. If any one of the above conditions is not true, the 82551IT uses the MW command MWI cycle has ...

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The 82551IT asserts the CLK_RUN# signal to indicate that the PCI clock must prevent the host from stopping or to request that the host restore the clock if it was previously stopped. Proper operation requires that the system latency ...

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Networking Silicon clock signal suspension using the Clockrun signal mechanism. The 82551IT supports a dynamic standby mode. In this mode, the 82551IT is able to save almost as much power as it does in the static power-down states. ...

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Auxiliary Power Signal The 82551IT senses whether it is connected to the PCI power supply auxiliary power supply (V ) through the FLA1/AUXPWR pin. The auxiliary power detection pin (multiplexed AUX with FLA1) is sampled when ...

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Networking Silicon If PME# is enabled (in the PCI power management registers), the RST# signal does not affect any PME# related circuits (in other words, the PCI power management registers, and the wake-up packet would not be affected). ...

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The following tables list the functionality at the different power states for the 82551IT. Table 11. Functionality at the Different Power States Power State D0u D0a (with power) Dx (x>0 without PME#) 5.3.2 Wake-up Events There are ...

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Networking Silicon 5.3.2.2 Link Status Change Event The 82551IT link status indication circuit is capable of issuing a PME on a link status change from a valid link to an invalid link condition or vice versa. The 82551IT ...

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All accesses, either read or write, are preceded by a command instruction to the device. The address field is six bits for a 64-register EEPROM or eight bits for a 256-register EEPROM. The end of the address field is indicated ...

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Networking Silicon 5.5.1 EEPROM Address Map Table 12 lists the EEPROM address map for the 82551IT Fast Ethernet Controller. Table 12. 82551IT EEPROM Address Map Word 00h Ethernet Individual Address Byte 2 01h Ethernet Individual Address Byte 4 ...

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Full Duplex When operating in full duplex mode the 82551IT can transmit and receive frames simultaneously. Transmission starts regardless of the state of the internal receive path. Reception starts when the internal PHY detects a valid frame on the ...

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Networking Silicon 5.7 Media Independent Interface (MII) Management Interface The MII management interface allows the CPU to control the PHY unit through a control register in the 82551IT. This allows the software driver to place the PHY in ...

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Physical Layer Functional Description 6.1 100BASE-TX PHY Unit 6.1.1 100BASE-TX Transmit Clock Generation A 25 MHz crystal MHz oscillator is used to drive the PHY unit’s X1 and X2 pins. The PHY unit derives its internal ...

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Networking Silicon 6.1.4 100BASE-TX Link Integrity Auto-Negotiation The 82551IT Auto-Negotiation function automatically configures the device to the technology, media, and speed to operate with its link partner. Auto-Negotiation is described in IEEE specification 802.3u, clause 28. The PHY ...

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Link Integrity and Full Duplex The link integrity in 10 Mbps works with link pulses. The PHY unit senses and differentiates those link pulses from fast link pulses and from 100BASE-TX idles. The link beat pulse is also ...

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Networking Silicon Figure 11. Auto-Negotiation and Parallel Detect Auto-Negotiation capable = 0 6.4 LED Description The PHY unit supports three LED pins to indicate link status, network activity and network speed. Each pin can source 10 mA. • ...

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Figure 12. Two and Three LED Schematic Diagram Datasheet LILED# R ACTLED# SPDLED# 82551IT LILED ACTLED# SPDLED# Networking Silicon — 82551IT vcc ...

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Configuration Registers The 82551IT acts as both a master and a slave on the PCI bus master, the 82551IT interacts with the system main memory to access data for transmission or deposit received data slave, ...

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Networking Silicon 7.1.2 PCI Command Register The 82551IT Command register at word address 04h in the PCI configuration space provides control over the 82551IT’s ability to generate and respond to PCI cycles register, the 82551IT is logically disconnected ...

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PCI Status Register The 82551IT Status register is used to record status information for PCI bus related events. The format of this register is shown in the figure below. Figure 15. PCI Status Register Detected Parity Error Signaled System ...

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Networking Silicon Table 14. PCI Status Register Bits Bits Name 24 Parity Error Detected 23 Fast Back-to-Back 20 Capabilities List 19:16 Reserved 44 Description This bit indicates whether a parity error has been detected. This bit is set ...

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PCI Revision ID Register The Revision 8-bit read only register. The three least significant bits of the Revision ID can be overridden by the ID and Revision ID fields in the EEPROM Interface”). The default values ...

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Networking Silicon 7.1.9 PCI Base Address Registers One of the most important functions for enabling superior configurability and ease of use is the ability to relocate PCI devices in address spaces. The 82551IT contains three types of Base ...

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CSR Memory Mapped Base Address Register The 82551IT requires one BAR for memory mapping. Software determines which BAR, memory or I/O, is used to access the 82551IT CSR registers. The memory space for the 82551IT CSR Memory Mapped BAR ...

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Networking Silicon The 82551IT provides support for configurable Subsystem Vendor ID and Subsystem ID fields. After hardware reset is de-asserted, the 82551IT automatically reads addresses Ah through Ch of the EEPROM. The first of these 16-bit values is ...

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Minimum Grant Register The Minimum Grant (Min_Gnt) register is an optional read only register for bus masters and is not applicable to non-master devices. It defines the amount of time the bus master wants to retain PCI bus ownership ...

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Networking Silicon Table 17. Power Management Capability Register Bits Default 20 0b (PCI 18:16 010b 7.1.20 Power Management Control/Status Register (PMCSR) The Power Management Control/Status is a word register used to determine and change ...

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Data Register The data register is an 8-bit read only register that provides a mechanism for the 82551IT to report state dependent maximum power consumption and heat dissipation. The value reported in this register depends on the value written ...

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Control/Status Registers 8.1 LAN (Ethernet) Control/Status Registers The 82551IT’s Control/Status Register (CSR) is shown in the figure Figure 19. Control/Status Register D31 Upper Word SCB Command Word EEPROM Control Register PMDR Reserved NOTE: In Figure 19 above, SCB is ...

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Networking Silicon MDI Control Register: The MDI Control register allows the CPU to read and write information from the PHY unit (or an external PHY component) through the Management Data Interface. Receive DMA Byte Count: The Receive DMA ...

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Table 20. System Control Block Status Word Bits Name 7:6 CUS 5:2 RUS 1:0 Reserved 8.1.2 System Control Block Command Word Commands for the 82551IT’s Command and Receive units are placed in this register by the CPU. Table 21. System ...

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Networking Silicon 8.1.6 EEPROM Control Register The EEPROM Control Register is a 32-bit field that enables a read from and a write to the external EEPROM. 8.1.7 Management Data Interface Control Register The Management Data Interface (MDI) Control ...

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Statistical Counters The 82551IT provides information for network management statistics by providing on-chip statistical counters that count a variety of events associated with both transmit and receive. The counters are updated by the 82551IT when it completes the processing ...

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Networking Silicon Table 23. Statistical Counters ID Counter 44 Receive Alignment Errors 48 Receive Resource Errors 52 Receive Overrun Errors 56 Receive Collision Detect (CDT) 60 Receive Short Frame Errors 64 Flow Control Transmit Pause 68 Flow Control ...

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The Statistical Counters are initially set to zero by the 82551IT after reset. They cannot be preset to anything other than zero. The 82551IT increments the counters by internally reading them, incrementing them and writing them back. This process is ...

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PHY Unit Registers The 82551IT provides status and accepts management information via the Management Data Interface (MDI) within the CSR space. Acronyms mentioned in the registers are defined as follows self cleared RO - read only E ...

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Networking Silicon Table 24. Register 0: Control Bit(s) Name 11 Power-Down 10 Reserved 9 Restart Auto- Negotiation 8 Duplex Mode 7 Collision Test 6:0 Reserved 9.1.2 Register 1: Status Register Table 25. Register 1: Status Bit(s) Name 15 ...

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Table 25. Register 1: Status Bit(s) Name 3 Auto-Negotiation Ability 2 Link Status 1 Jabber Detect 0 Extended Capability 9.1.3 Register 2: PHY Identifier Register Table 26. Register 2: PHY Identifier Bit(s) Name 15:0 PHY ID (high byte) 9.1.4 Register ...

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Networking Silicon 9.1.6 Register 5: Auto-Negotiation Link Partner Ability Register Table 29. Auto-Negotiation Link Partner Ability Bit(s) Name 15 Next Page 14 Acknowledge 13 Remote Fault 12:5 Technology Ability Field 4:0 Selector Field 9.1.7 Register 6: Auto-Negotiation Expansion ...

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MDI Register 16:31 9.3.1 Register 16: PHY Unit Status and Control Register Table 31. PHY Unit Status and Control Bit(s) Name 15:14 Reserved 13 Carrier Sense Disconnect Control 12 Transmit Flow Control Disable 11 Receive De- Serializer In-Sync Indication ...

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Networking Silicon Table 32. Register 17: PHY Unit Special Control Bit(s) Name 12 Force 34 Transmit Pattern 11 Good Link 10 Reserved 9 Transmit Carrier Sense Disable 8 Disable Dynamic Power-Down 7 Auto-Negotiation Loopback 6 MDI Tri-State 5 ...

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Register 20: 100BASE-TX Receive Disconnect Counter Table 35. Register 20: 100BASE-TX Receive Disconnect Counter Bit(s) Name 15:0 Disconnect Event 9.3.6 Register 21: 100BASE-TX Receive Error Frame Counter Table 36. Register 21: 100BASE-TX Receive Error Frame Counter Bit(s) Name 15:0 ...

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Networking Silicon 9.3.10 Register 25: 10BASE-T Transmit Jabber Detect Counter Table 40. Register 25: 10BASE-T Transmit Jabber Detect Counter Bit(s) Name 15:0 Jabber Detect Counter 9.3.11 Register 26: Equalizer Control and Status Register Table 41. Register 26: Equalizer ...

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Register 28: MDI/MDI-X Control Register Table 43. Register 28: MDI/MDI-X Control Bit(s) Name 15:8 Reserved Auto Switch 7 Enable 6 Switch 5 Status Auto Switch 4 Complete 3:0 Resolution Timer 9.3.14 Register 29: Hardware Integrity Control Register Table 44. ...

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Networking Silicon Table 44. Register 29: Hardware Integrity Control Bit(s) Name 12:11 Reserved 10:9 LowZ/HighZ 8:0 Distance 70 Description These bits are reserved and should be set to 0b. This field of bits indicates either a short (Low ...

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Test Port Functionality 10.1 Introduction The 82551IT’s XOR Tree Test Access Port (TAP) is the access point for test data to and from the device. The port provides the ability to perform basic production level testing. 10.2 Test ...

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Networking Silicon 10.2.2 XOR Tree The XOR Tree test mode is the most useful of the asynchronous test modes. It enables the placement of the 82551IT to be validated at board test. The XOR Tree was chosen for ...

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Table 45. XOR Tree Chains (XOR Tree Output) Datasheet Chain Order Chain 1 (FLOE#) 22 PAR 23 AD[16] 24 C/BE#[1] 25 AD[15] 26 AD[14] 27 AD[13] 28 AD[12] 29 AD[11] 30 AD[10] 31 AD[9] 32 AD[8] 33 C/BE#[0] 34 AD[7] ...

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Electrical and Timing Specifications Note: This section contains information on products in sampling and early production phase of development. Do not finalize a design with this information. Revised information will be published when the product becomes available. 11.1 Absolute ...

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Networking Silicon 11.2 DC Specifications Table 46. General DC Specifications Symbol Parameter V Supply Voltage CC Periphery Clamp V IO Voltage Power Supply (10BASE- Power Supply (100BASE-TX) NOTES: 1. Preferably, VIO should ± ...

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The 82551IT supports PCI interface standards. In the PCI mode five volts tolerant and supports both 5 V and 3.3 V signaling environments. Table 47. PCI Interface DC Specifications Symbol Parameter V Input High Voltage IHP V Input ...

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Networking Silicon Table 49. LED Voltage/Current Characteristics Symbol Parameter V Output High Voltage OHLED V Output Low Voltage OLLED Table 50. 100BASE-TX Voltage/Current Characteristics Symbol Parameter Input Differential R ID100 Impedance Input Differential V IDA100 Accept Peak Voltage ...

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Table 51. 10BASE-T Voltage/Current Characteristics Symbol Parameter Input Differential R ID10 Impedance Input Differential V IDA10 Accept Peak Voltage Input Differential V IDR10 Reject Peak Voltage Input Common Mode V ICM10 Voltage Output Differential V OD10 Peak Voltage Line Driver ...

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Networking Silicon 11.3 AC Specifications Table 54. AC Specifications for PCI Signaling Symbol Parameter Switching Current High I OH(AC) (Test Point) Switching Current Low I OL(AC) (Test Point) Low Clamp I CL Current High Clamp I CH Current ...

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Timing Specifications 11.4.1 Clocks Specifications 11.4.1.1 PCI Clock Specifications The 82551IT uses the PCI Clock signal directly. measurement points for the PCI Clock signal. Figure 20. PCI Clock Waveform 0.475V CC 0.4V CC 0.325V CC Table 55. PCI Clock ...

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Networking Silicon 11.4.2 Timing Parameters 11.4.2.1 Measurement and Test Conditions Figure 21, Figure 22, and done. The component test guarantees that all timings are met with minimum clock slew rate (slowest edge) and voltage swing. The design must ...

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Table 57. Measure and Test Condition Parameters V step V step Input Signal Edge NOTE: Input test is done with 0.1V for testing input timing. 11.4.2.2 PCI Timings Table 58. PCI Timing Parameters Symbol T14 t PCI CLK to Signal ...

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Networking Silicon Table 59. Flash Timing Parameters Symbol T35 t Flash Read/Write Cycle Time flrwc T36 t FLA to Read FLD Setup Time flacc T37 t FLCS# to Read FLD Setup Time flce T38 t FLOE# Active to ...

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Figure 23. Flash Timings for a Read Cycle FLADDR FLCS# FLOE# FLDATA-R IOCHRDY Figure 24. Flash Timings for a Write Cycle FLADDR FLCS# FLWE# FLDATA-W IOCHRDY Datasheet Networking Silicon — 82551IT Address Stable T35 T37 T38 T36 Data In T49 ...

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Networking Silicon 11.4.2.4 EEPROM Interface Timings The 82551IT is designed to support a standard64x16 or 256x16 serial EEPROM. the timing parameters for the EEPROM interface signals. The timing parameters are shown in Figure 25. Table 60. EEPROM Timing ...

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PHY Timings Table 61. 10BASE-T Normal Link Pulse (NLP) Timing Parameters Symbol T56 T NLP Width nlp_wid T57 T NLP Period nlp_per Figure 26. 10BASE-T Normal Link Pulse (NLP) Timings Normal Link Pulse Table 62. Auto-Negotiation Fast Link Pulse ...

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Networking Silicon Table 63. 100Base-TX Transmitter AC Specification Symbol TDP/TDN Differential T64 T jit Output Peak Jitter 88 Parameter Condition Min HLS Data Typ Max Units 1400 ps Datasheet ...

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... Substrate change from 0. 0.32 mm Note: No changes to existing soldering processes are needed for the 0.32 mm substrate change. Datasheet Networking Silicon — 82551IT ® device packaging is available in the Intel Packaging 1.56 +/-0.19 0.85 0.40 +/-0.10 Seating Plate Note: All dimensions are in millimeters. o ...

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Networking Silicon Figure 29. 196 PBGA Package Pad Detail 0.45 Solder Resist Opening 0.60 Metal Diameter As illustrated in Figure 0.60 mm and the opening in the solder mask is 0.45 mm. The nominal ball sphere diameter is ...

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Pinout Information 12.2.1 Pin Assignments Table 62. Pin Assignments Pin A10 A13 B10 B13 RBIAS100 C10 C13 D10 D13 E10 E13 ...

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Networking Silicon Table 62. Pin Assignments Pin G13 H10 H13 J10 J13 K10 K13 L10 L13 M1 M4 C/BE#[0] M7 M10 FLA15/EESK M13 ...

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Ball Grid Array Diagram Figure 30. Ball Grid Array Diagram AD[22] AD[21] 2 SERR# AD[23] RST# 3 VCC VSSPP REQ# C/BE#[3] 4 IDSEL AD[24] 5 AD[25] AD[26 PME# AD[27] AD[28] VCC VSSPP ...

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Networking Silicon 13.0 Reference Schematics This section shows a 10/100 Mbps design using the 82551IT Fast Ethernet PCI Controller. 94 Datasheet ...

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A12 C11 B11 TDP C13 TDN C14 RDP E13 E14 RDN Keep all termination resistors as close to the 82551 as ...

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... Pulldown resistors are used on strapped pins to enable the NAND tree test mode to work. The value ohm was chosen strictly on the basis of Intel’s test fixturing requirements Other values can be used, but it is recommended that resistors be used other than hard strapping the pins. F ...